sdsdi_rxtx_cyclone_board.qsf

DVB系统的SDI数据数据传输接口

# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		sdsdi_rxtx_cyclone_board_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 2.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:58:29  FEBRUARY 10, 2004"
set_global_assignment -name LAST_QUARTUS_VERSION 4.1
set_parameter -name CARRY_CHAIN MANUAL
set_parameter -name CASCADE_CHAIN MANUAL
set_parameter -name OPTIMIZE_FOR_SPEED 1
set_parameter -name STYLE FAST
set_global_assignment -name VERILOG_FILE ../../source/sdi_transmit/sdi_makeframe.v
set_global_assignment -name VERILOG_FILE ../../source/sdi_transmit/gen_patho.v
set_global_assignment -name VERILOG_FILE ../../source/sdi_transmit/gen_colorbar.v
set_global_assignment -name VERILOG_FILE ../../source/sdi_transmit/pattern_gen.v
set_global_assignment -name VERILOG_FILE ../../source/sdi_transmit/sdi_scrambler.v
set_global_assignment -name VERILOG_FILE ../../source/sdi_transmit/p2s.v
set_global_assignment -name VERILOG_FILE ../../source/sdi_transmit/hdsdi_trsmatch.v
set_global_assignment -name VERILOG_FILE ../../source/sdi_transmit/hdsdi_crc.v
set_global_assignment -name VERILOG_FILE ../../source/sdi_receive/sdi_aligner.v
set_global_assignment -name VERILOG_FILE ../../source/sdi_receive/sdi_descrambler.v
set_global_assignment -name VERILOG_FILE ../../source/sdi_receive/sdsdi_receive.v
set_global_assignment -name VERILOG_FILE ../../source/sdi_receive/hdsdi_extract_ln.v
set_global_assignment -name VERILOG_FILE ../../source/sdi_receive/s2p.v
set_global_assignment -name VERILOG_FILE ../../source/sdi_receive/gxb_rxsample.v
set_global_assignment -name VERILOG_FILE ../../source/demo/sdsdi_io_interface.v
set_global_assignment -name VERILOG_FILE ../../source/demo/fifo_256x20.v
set_global_assignment -name VERILOG_FILE ../../source/demo/sync.v
set_global_assignment -name VERILOG_FILE ../../source/demo/freq_trans.v
set_global_assignment -name VERILOG_FILE ../../source/demo/sclk_pll_x50_4.v
set_global_assignment -name VERILOG_FILE ../../source/demo/sclk_pll_x30_4.v
set_global_assignment -name VERILOG_FILE ../../source/demo/sclk_pll_x10.v
set_global_assignment -name VERILOG_FILE ../../source/demo/sdsdi_rxtx.v
set_global_assignment -name VERILOG_FILE ../../source/cyclone_board/sdsdi_rxtx_cyclone_board.v
set_global_assignment -name SIGNALTAP_FILE debug.stp

# Pin & Location Assignments
# ==========================
set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED"
set_location_assignment LC_X2_Y19_N0 -to "sdsdi_rxtx:u_demo\|sdsdi_io_interface:u_io_interface\|s2p:u_s2p\|sample_a\[0\]"
set_location_assignment LC_X3_Y19_N0 -to "sdsdi_rxtx:u_demo\|sdsdi_io_interface:u_io_interface\|s2p:u_s2p\|sample_b\[0\]"
set_location_assignment LC_X2_Y19_N1 -to "sdsdi_rxtx:u_demo\|sdsdi_io_interface:u_io_interface\|s2p:u_s2p\|sample_c\[0\]"
set_location_assignment LC_X3_Y19_N1 -to "sdsdi_rxtx:u_demo\|sdsdi_io_interface:u_io_interface\|s2p:u_s2p\|sample_d\[0\]"
set_location_assignment PIN_5 -to button\[0\]
set_location_assignment PIN_6 -to button\[1\]
set_location_assignment PIN_7 -to button\[2\]
set_location_assignment PIN_10 -to button\[3\]
set_location_assignment PIN_27 -to header\[0\]
set_location_assignment PIN_39 -to header\[10\]
set_location_assignment PIN_40 -to header\[11\]
set_location_assignment PIN_41 -to header\[12\]
set_location_assignment PIN_42 -to header\[13\]
set_location_assignment PIN_47 -to header\[14\]
set_location_assignment PIN_48 -to header\[15\]
set_location_assignment PIN_49 -to header\[16\]
set_location_assignment PIN_50 -to header\[17\]
set_location_assignment PIN_51 -to header\[18\]
set_location_assignment PIN_52 -to header\[19\]
set_location_assignment PIN_28 -to header\[1\]
set_location_assignment PIN_53 -to header\[20\]
set_location_assignment PIN_56 -to header\[21\]
set_location_assignment PIN_57 -to header\[22\]
set_location_assignment PIN_58 -to header\[23\]
set_location_assignment PIN_59 -to header\[24\]
set_location_assignment PIN_60 -to header\[25\]
set_location_assignment PIN_61 -to header\[26\]
set_location_assignment PIN_62 -to header\[27\]
set_location_assignment PIN_67 -to header\[28\]
set_location_assignment PIN_68 -to header\[29\]
set_location_assignment PIN_31 -to header\[2\]
set_location_assignment PIN_69 -to header\[30\]
set_location_assignment PIN_70 -to header\[31\]
set_location_assignment PIN_32 -to header\[3\]
set_location_assignment PIN_33 -to header\[4\]
set_location_assignment PIN_34 -to header\[5\]
set_location_assignment PIN_35 -to header\[6\]
set_location_assignment PIN_36 -to header\[7\]
set_location_assignment PIN_37 -to header\[8\]
set_location_assignment PIN_38 -to header\[9\]
set_location_assignment PIN_1 -to led\[0\]
set_location_assignment PIN_2 -to led\[1\]
set_location_assignment PIN_3 -to led\[2\]
set_location_assignment PIN_4 -to led\[3\]
set_location_assignment PIN_144 -to rsds\[0\]
set_location_assignment PIN_142 -to rsds\[1\]
set_location_assignment PIN_140 -to rsds\[2\]
set_location_assignment PIN_131 -to rsds\[3\]
set_location_assignment PIN_129 -to rsds\[4\]
set_location_assignment PIN_124 -to rsds\[5\]
set_location_assignment PIN_114 -to rsds\[6\]
set_location_assignment PIN_112 -to rsds\[7\]
set_location_assignment PIN_110 -to rsds\[8\]
set_location_assignment PIN_108 -to rsds_clk
set_location_assignment PIN_71 -to rsds_start
set_location_assignment PIN_26 -to rx_pclk_out
set_location_assignment PIN_144 -to sdi_rx
set_location_assignment PIN_108 -to sdi_tx
set_location_assignment PIN_72 -to switch\[0\]
set_location_assignment PIN_73 -to switch\[1\]
set_location_assignment PIN_74 -to switch\[2\]
set_location_assignment PIN_75 -to switch\[3\]
set_location_assignment PIN_76 -to switch\[4\]
set_location_assignment PIN_77 -to switch\[5\]
set_location_assignment PIN_78 -to switch\[6\]
set_location_assignment PIN_96 -to switch\[7\]
set_location_assignment PIN_11 -to tx_pclk_out
set_location_assignment PIN_16 -to clk0
set_location_assignment PIN_17 -to clk1
set_location_assignment PIN_93 -to clk2
set_location_assignment PIN_92 -to clk3

# Timing Assignments
# ==================
set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name SPEED_DISK_USAGE_TRADEOFF SMART
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name STATE_MACHINE_PROCESSING AUTO
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name ADV_NETLIST_OPT_RETIME_CORE_AND_IO OFF
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF
set_global_assignment -name AUTO_RESOURCE_SHARING ON
set_global_assignment -name TOP_LEVEL_ENTITY sdsdi_rxtx_cyclone_board
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name AUTO_ENABLE_SMART_COMPILE on
set_global_assignment -name SIMGEN_PARAMETER "CBX_HDL_LANGUAGE=vhdl"
set_global_assignment -name SIMGEN_BLACKBOX_FILE "c:/program files/altera/quartus_4.0/libraries/megafunctions/simgen_blackbox_list.txt"

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1C6T144C6
set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "ACTIVE SERIAL"
set_global_assignment -name AUTO_RESTART_CONFIGURATION ON
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION"
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name INC_PLC_MODE OFF
set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF
set_instance_assignment -name IO_STANDARD LVTTL -to button\[0\]
set_instance_assignment -name IO_STANDARD LVTTL -to button\[1\]
set_instance_assignment -name IO_STANDARD LVTTL -to button\[2\]
set_instance_assignment -name IO_STANDARD LVTTL -to button\[3\]
set_instance_assignment -name IO_STANDARD LVTTL -to header\[0\]
set_instance_assignment -name IO_STANDARD LVTTL -to header\[10\]
set_instance_assignment -name IO_STANDARD LVTTL -to header\[11\]
set_instance_assignment -name IO_STANDARD LVTTL -to header\[12\]
set_instance_assignment -name IO_STANDARD LVTTL -to header\[13\]
set_instance_assignment -name IO_STANDARD LVTTL -to header\[14\]
set_instance_assignment -name IO_STANDARD LVTTL -to header\[15\]
set_instance_assignment -name IO_STANDARD LVTTL -to header\[16\]
set_instance_assignment -name IO_STANDARD LVTTL -to header\[17\]
set_instance_assignment -name IO_STANDARD LVTTL -to header\[18\]
set_instance_assignment -name IO_STANDARD LVTTL -to header\[19\]