📄 addrgenerate.vhd
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library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity AddrGenerate is port ( SdramClk: in std_logic; --时钟信号 reqack: in std_logic; --操作结束标志 Reset: in std_logic; --复位信号 --cmdlengthcount: in std_logic_vector(9 downto 0); --计数器值 --PageWrfstAdr: in std_logic_vector(11 downto 0); --??页读首地址,固定 PageWrfstAdr: in std_logic_vector(13 downto 0); --??页读首地址,固定 --PageRdfstAdr: in std_logic_vector(11 downto 0); --??页写首地址,固定 PageRdfstAdr: in std_logic_vector(13 downto 0); OperationReq: in std_logic_vector(2 downto 0); --操作码 PageWeAdrSet: in std_logic; --页读首地址复位信号 PageRdAdrSet: in std_logic; --页写首地址复位信号 ADDR: out std_logic_vector(22 downto 0); --??地址总线 HostRd : in std_logic; HostAdr: in std_logic_vector(22 downto 0); --??随机读写地址 FIFO1Data: in std_logic_vector(15 downto 0); --FIFO1输出数据 DataOut: out std_logic_vector(15 downto 0); --数据总线输出 FIFO2Data: out std_logic_vector(15 downto 0); --FIFO2输入数据 DataIn: in std_logic_vector(15 downto 0); --数据总线输入 HostDataout: out std_logic_vector(15 downto 0); --随机读写数据 HostDatain: in std_logic_vector(15 downto 0); --ackcount : in std_logic_vector(2 downto 0); sdramin : out std_logic_vector(15 downto 0);-- cmd : in std_logic_vector(2 downto 0); count5 : in std_logic_vector(2 downto 0); count3 : in std_logic_vector(2 downto 0) );end AddrGenerate;architecture rtl of AddrGenerate is signal randomaddr:std_logic_vector(22 downto 0):="00000000000000000000000"; --?? signal clk:std_logic; signal writeaddr:std_logic_vector(13 downto 0):="00000000000000";--?? signal readaddr:std_logic_vector(13 downto 0):="00000000000000"; --?? begin clk<=SdramClk; randomaddr<=HostAdr; sdramin <= DataIn; DataOut <= HostDatain when OperationReq="011" else FIFO1Data; process(clk,OperationReq,writeaddr,readaddr,PageWeAdrSet,PageRdAdrSet,reset,HostRd) begin if (reset='0')then --复位 FIFO2Data<="0000000000000000"; HostDataout<="0000000000000000"; ADDR<="00000000000000000000000"; --?? writeaddr<="00000000000000"; readaddr<= "00000000000000"; elsif (clk'event and clk='1')then -------------------页读页写首地址复位操作------------------------------------------- if (PageWeAdrSet='1')then writeaddr<=PageWrfstAdr; end if; if (PageRdAdrSet='1')then readaddr<=PageRdfstAdr; end if; case OperationReq is -------------------无操作Idle--------------------------------------- when "000"=> ADDR<= "00000000000000000000000";-------------------页写地址产生------------------------------------- when "001" => --if(cmdlengthcount>="0000000001")then if(count5 ="001") then ADDR<=writeaddr & "000000000"; --?? end if; if(reqack='1')then writeaddr<=writeaddr+1; --页写地址加1 end if;-------------------页读地址产生----------------------------------------- when "010" => --if(cmdlengthcount>="0000000001")then if(count5 ="001") then FIFO2Data<= DataIn; ADDR<= readaddr & "000000000"; --?? end if; if(reqack='1')then readaddr<=readaddr+1; --页读地址加1 end if;-------------------随机写地址产生--------------------------------------- when "011" => --if(cmdlengthcount>="0000000001")then if(count5 ="001") then ADDR<=randomaddr; end if;-------------------随机读地址产生--------------------------------------- when "100" => --if(cmdlengthcount>="0000000001")then --if(count5 ="001") then if(count3 = "101") then if(HostRd= '0') then HostDataout <= DataIn; end if; end if; ADDR <= randomaddr; -- end if;-------------------配置页模式----------------------------------- when "101" =>------------------------------------------------ --load_mode_reg -- if(count1 = "001") then-- ADDR<= "00000000000000000100111"; -- end if; --load refresh reg2--05f6-- if(count2 = "001") then -- ADDR<= "00000000000000111111010"; -- end if; ------------------------------------------------- --if(cmd = "101" and ackcount="011" ) then --load_mode_reg if(count5 ="001") then ADDR<= "00000000000000000100111"; end if; -------------------配置随机模式----------------------------------- when "110" => --if(cmd = "101" and ackcount="011" ) then if(count5 ="001") then ADDR<= "00000000000000000100000"; end if; when others =>NULL; end case; end if;end process;end rtl;
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