tb_topcon.vhd

sdram控制器

--###############################################################################
--
--  LOGIC CORE:          SDR SDRAM topController 							
--  MODULE NAME:         tb_topCon()                	
--  date:		 2006.8.22
--  REVISION HISTORY:  
--  FUNCTIONAL DESCRIPTION:
--
--  This module is the state_machine for the SDR SDRAM controller.
--  Copyright (C) 1991-2000 
--##############################################################################
-- VHDL Test Bench Created from source file topcon.vhd -- 08/19/06  15:03:16
--
-- Notes: 
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Lattice recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "source->import"
-- menu in the ispLEVER Project Navigator to import the testbench.
-- Then edit the user defined section below, adding code to generate the 
-- stimulus for your design.

LIBRARY ieee;
LIBRARY generics;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE generics.components.ALL;
--use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS 

	component mt48lc8m16a2
 	PORT (
        	Dq    : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) := (OTHERS => 'Z');
        	Addr  : IN    STD_LOGIC_VECTOR (11 DOWNTO 0) := (OTHERS => '0');
        	Ba    : IN    STD_LOGIC_VECTOR := "00";
        	Clk   : IN    STD_LOGIC := '0';
        	Cke   : IN    STD_LOGIC := '0';
        	Cs_n  : IN    STD_LOGIC := '1';
        	Ras_n : IN    STD_LOGIC := '0';
        	Cas_n : IN    STD_LOGIC := '0';
        	We_n  : IN    STD_LOGIC := '0';
        	Dqm   : IN    STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0')
    		);
	END component;
	
	COMPONENT topcon1
	port (
               	clk            	: in      std_logic;                            --!系统时钟由 pll产生，100mhz                 	               	
		clkop          	: out      std_logic;
	        reset          	: in      std_logic;
		pllreset        : in      std_logic;
		fifo1rden       : out     std_logic;			       --fifo的使能信号高电平有效
	        fifo2wren       : out     std_logic;
		hostdataen      : out     std_logic;	        
		HostAdr         : in      std_logic_vector(22 downto 0);	--???外部提供的随机地址信号
		HostDataout     : out     std_logic_vector(15 downto 0);	--随机读写数据
		HostDatain      : IN      std_logic_vector(15 downto 0);	--随机读写数据		
		DataWr		: in	  std_logic_vector(15 downto 0);	--!give to add_mode外部输入数据，可连接前端fifo，或选通后接主机数据总线
		DataRd		: out     std_logic_vector(15 downto 0);	--外部输出数据，可连接后端fifo，或选通后接主机数据总线
		reqack       	: out 	  std_logic;
		PageWeAdrSet    : in 	  std_logic;		                --!页写首地址复位信号
		PageRdAdrSet    : in 	  std_logic;                           	--!页读首地址复位信号          	
		FIFO1AlmostF    : IN 	  std_logic;
		FIFO2AlmostE    : IN 	  std_logic;
		TransferMode 	: IN 	  std_logic;
		HostWr 		: IN 	  std_logic;
		HostRd 		: IN 	  std_logic;		
		LOCK		: out 	  std_logic;
		CLKOS		: out 	  std_logic;					       
		SA              : out     std_logic_vector(11 downto 0);        --???SDRAM address output
         	BA              : out     std_logic_vector(1 downto 0);         --SDRAM bank address
		CS_N            : out     std_logic;                		--SDRAM Chip Selects
         	CKE             : out     std_logic;                            --SDRAM clock enable
         	RAS_N           : out     std_logic;                            --SDRAM Row address Strobe
         	CAS_N           : out     std_logic;                            --SDRAM Column address Strobe
         	WE_N            : out     std_logic;                            --SDRAM write enable
         	DQ              : inout   std_logic_vector(15 downto 0);        --！SDRAM data bus
         	DQM             : out     std_logic_vector(1 downto 0) ;  	--SDRAM data mask lines
------------------------------test use-----------------------------------
--		operationreqt : 	out std_logic_vector(2 downto 0);
--		cmdt       	: out     std_logic_vector(2 downto 0);         --输出当前的状态
--		count1         	: out 	  std_logic_vector(2 downto 0);
--		sdramint        : out     std_logic_vector(15 downto 0);	--接口输入数据总线；
--		sdramoutt   	: out     std_logic_vector(15 downto 0);	--接口输出数据总线
		CMDACKtt	: out     std_logic
--		cmdlengthcount	: out     std_logic_vector(9 downto 0);
--		tcmdlengthcount : out      std_logic_vector(9 downto 0)
		);
	END COMPONENT;

	SIGNAL clk :  std_logic;	
	SIGNAL reset :  std_logic;
	SIGNAL fifo1rden :  std_logic;
	SIGNAL fifo2wren :  std_logic;
	SIGNAL hostdataen :  std_logic;
	SIGNAL HostAdr :  std_logic_vector(22 downto 0):="00000000000000000000000";
	SIGNAL HostDataout :  std_logic_vector(15 downto 0):="0000000000000000";
	SIGNAL HostDatain :  std_logic_vector(15 downto 0):="0000000000000000";
	SIGNAL DataWri :  std_logic_vector(15 downto 0):="0000000000000000";
	SIGNAL DataRd :  std_logic_vector(15 downto 0):="0000000000000000";
	SIGNAL PageWeAdrSet :  std_logic:='0';
	SIGNAL PageRdAdrSet :  std_logic:='0';
	SIGNAL FIFO1AlmostF :  std_logic:='0';
	SIGNAL FIFO2AlmostE :  std_logic:='1';
	SIGNAL TransferMode :  std_logic;
	SIGNAL HostWr :  std_logic:='1';
	SIGNAL HostRd :  std_logic:='1';
	signal	reqacki       :   std_logic;
	SIGNAL cmdlengthcount:      std_logic_vector(9 downto 0):="0000000000";
	signal count1         :  std_logic_vector(2 downto 0):="000";
	SIGNAL LOCK		:  std_logic;
	SIGNAL	CLKOS		:  std_logic;
	SIGNAL	pllreset          	:       std_logic;
	SIGNAL SA :  std_logic_vector(11 downto 0):="000000000000";
	SIGNAL BA :  std_logic_vector(1 downto 0);
	SIGNAL CS_N :  std_logic;
	SIGNAL CKE :  std_logic;
	SIGNAL RAS_N :  std_logic;
	SIGNAL CAS_N :  std_logic;
	SIGNAL WE_N :  std_logic;
	SIGNAL DQ :  std_logic_vector(15 downto 0):="0000000000000000";
	SIGNAL DQM :  std_logic_vector(1 downto 0):="00";
	signal cmdti       	:    std_logic_vector(2 downto 0):="000";         --输出当前的状态
	signal CMDACKtti	:      std_logic;
	signal sdraminti          :       std_logic_vector(15 downto 0):="0000000000000000";	--接口输入数据总线；
	signal	sdramoutti   	:      std_logic_vector(15 downto 0):="0000000000000000";	--接口输出数据总线
	signal 	tcmdlengthcount :       std_logic_vector(9 downto 0);
	signal operationreqti : 	 std_logic_vector(2 downto 0);
	signal clkopi          	:       std_logic;
--	procedure   page_write_burst(
--	           start_value         : std_logic_vector(15 downto 0);
  --                 len                 : integer;
    --               signal dataout      : out std_logic_vector(15 downto 0);
      --             signal fifoent      : in std_logic
        --      ) is

  --       variable i : integer;
  --       begin
  --            dataout <= start_value;                      
   --           if (fifoent = '1') then
   --           	for i in 1 to len loop                                         -- burst out len data cycles 
--	      	wait until (CLKOS'event and CLKOS = '1');
  --                 dataout <= start_value + i;
   --           	wait for 1 ns;
    --          	end loop;
--	      end if;       
-- 	end page_write_burst;

	procedure   write_burst(	           
                   signal dataout      : out std_logic_vector(15 downto 0):="0000000000000000";
                   signal HostAdr      : out std_logic_vector(22 downto 0)
              	) is

		variable i : integer;
		variable y : std_logic_vector(15 downto 0);
		begin              
	     		HostAdr <= "00000000000000000000001";
	     		dataout<=X"7777";                 
 	end write_burst;
	procedure   read_burst(	           
                   signal HostAdr      : out std_logic_vector(22 downto 0)
              	) is

         	variable i : integer;
         	begin              
              		HostAdr <= "00000000000000000000001";
	end read_burst;

	
BEGIN



B00: mt48lc8m16a2
	port map(
		Dq        =>   DQ(15 downto 0),
		Addr      =>   SA(11 downto 0),
		Ba        =>   BA,
		CLK       =>   CLKOS,
		Cke       =>   CKE,
		Cs_n      =>   CS_N,
		Cas_n     =>   CAS_N,
		Ras_n     =>   RAS_N,
		We_n      =>   WE_N,
		Dqm       =>   DQM(1 downto 0)
	);

-- *** Test Bench - User Defined Section ***
  	process
	begin
		clk <= '0';
		wait for 16 ns;
		clk <= '1';
		wait for 16 ns;
  	end process;
	pllreset <= '1','0' after 36 ns;--,'0' after 20ns;

  	reset <= '0','1' after 516 ns;--,'0' after 20ns;

	TransferMode <=	'1' ,	--1.Configure page mode

			'0' after 601 ns;	--1.Configure page mode

--			'1' after 11500 ns;	--4.Configure host mode

------页写－－－－
	PROCESS
	BEGIN
	WAIT FOR 1206 ns;
	PageWeAdrSet <= '1';
	FIFO1AlmostF <= '1';
	wait for 100 ns;
		PageWeAdrSet <= '0';
		FIFO1AlmostF <= '0';
	wait for 5000 ns;
	end process;
--------页读－－－－－－－－－－
	process
	begin
	WAIT FOR 1606 ns;
		PageRdAdrSet <= '1';
		FIFO2AlmostE <= '1';
	wait for 100 ns;
		PageRdAdrSet <= '0';
		FIFO2AlmostE <= '0';
	wait for 4600 ns;
	end process;	


-----随机操作----------
--	HostWr <='1' ,
--		'0' after 1501 ns,	--5.host write		
--		'1' after 1701 ns;
--	HostRd <='1' ,	
--		'0' after 1801 ns,	--6.host read	
--		'1' after 1991 ns;
--	write_burst( HostDatain,HostAdr);
--	read_burst( HostAdr);
--------页写读操作模块(实现)--------

	process (clkopi)
	begin
	if(reset ='0')	then
		DataWri<=X"0000";
	elsif rising_edge(clkopi) then
			if (fifo1rden= '1') then
                  		DataWri <= DataWri + 1 after 1 ns;
			end if;
	end if;			
	END PROCESS;
	

uuu: topcon1 PORT MAP(
		clk 		=> clk,
		clkop		=>clkopi,
		reset 		=> reset,			
		fifo1rden 	=> fifo1rden,
		fifo2wren 	=> fifo2wren,
		hostdataen 	=> hostdataen,
		HostAdr 	=> HostAdr,
		HostDataout 	=> HostDataout,
		HostDatain 	=> HostDatain,
		DataWr 		=> DataWri,
		DataRd 		=> DataRd,
		PageWeAdrSet 	=> PageWeAdrSet,
		PageRdAdrSet 	=> PageRdAdrSet,
		FIFO1AlmostF 	=> FIFO1AlmostF,
		FIFO2AlmostE 	=> FIFO2AlmostE,
		TransferMode 	=> TransferMode,
		HostWr 		=> HostWr,
		HostRd 		=> HostRd,
		LOCK		=> LOCK,
		CLKOS		=> CLKOS,
		pllreset        => pllreset,			
		SA 		=> SA,
		BA 		=> BA,
		CS_N 		=> CS_N,
		CKE 		=> CKE,
		RAS_N 		=> RAS_N,
		CAS_N 		=> CAS_N,
		WE_N 		=> WE_N,
		DQ 		=> DQ,
		DQM 		=> DQM,
----------------------------------------------
--		sdramint        => sdraminti,
--		sdramoutt   	=> sdramoutti,
--		cmdlengthcount	=> cmdlengthcount,
--		count1         	=> count1,
--		cmdt       	=> cmdti,
		reqack       	=> reqacki,
		CMDACKtt	=> CMDACKtti
--		operationreqt 	=>  operationreqti,
--		tcmdlengthcount => tcmdlengthcount
	);
-- *** End Test Bench - User Defined Section ***

END;