img.vhd

基于fpga和sopc的用VHDL语言编写的EDA的VGA彩条信号显示控制器

LIBRARY ieee;  --图象显示顶层程序
USE ieee.std_logic_1164.all; 
ENTITY img IS 
	port
	( clk50MHz :  IN  STD_LOGIC;
  		hs,	vs,	r, g, b :  OUT  STD_LOGIC );
END img;
ARCHITECTURE modelstru OF img IS 
 component vga640480                --VGA显示控制模块
	PORT(clk : IN STD_LOGIC;
		 rgbin : IN STD_LOGIC_VECTOR(2 downto 0);
		 hs, vs, r, g, b : OUT STD_LOGIC;
		 hcntout, vcntout : OUT STD_LOGIC_VECTOR(9 downto 0)	);
end component;
component imgrom                   --图象数据ROM，数据线3位；地址线12位
	PORT(inclock : IN STD_LOGIC;
		 address : IN STD_LOGIC_VECTOR(11 downto 0);
		 q : OUT STD_LOGIC_VECTOR(2 downto 0)	);
end component;
signal	rgb :  STD_LOGIC_VECTOR(2 downto 0);
signal	clk25MHz : std_logic;
signal	romaddr :  STD_LOGIC_VECTOR(11 downto 0);
signal	hpos, vpos	:  std_logic_vector(9 downto 0);
BEGIN 
romaddr <= vpos(5 downto 0) & hpos(5 downto 0);
process(clk50MHz) begin
if clk50MHz'event and clk50MHz = '1' then clk25MHz <= not clk25MHz ; end if;
end process;
i_vga640480 : vga640480 PORT MAP(clk => clk25MHz, rgbin => rgb, hs => hs, 
vs => vs, r => r, g => g, b => b, hcntout => hpos, vcntout => vpos);
i_rom : imgrom PORT MAP(inclock => clk25MHz, address => romaddr, q => rgb);
end;