freqtest.fit.eqn

基于fpga和sopc的用VHDL语言编写的EDA频率测试与FPGA单片机通讯

--DATA[11] is DATA[11] at LC_X34_Y16_N2
--operation mode is normal

DATA[11]_sload_eqn = DIN[3];
DATA[11] = DFFEA(DATA[11]_sload_eqn, GLOBAL(CLOCK3), VCC, , , , );


--DATA[10] is DATA[10] at LC_X33_Y16_N2
--operation mode is normal

DATA[10]_sload_eqn = DIN[2];
DATA[10] = DFFEA(DATA[10]_sload_eqn, GLOBAL(CLOCK3), VCC, , , , );


--DATA[9] is DATA[9] at LC_X34_Y16_N4
--operation mode is normal

DATA[9]_sload_eqn = DIN[1];
DATA[9] = DFFEA(DATA[9]_sload_eqn, GLOBAL(CLOCK3), VCC, , , , );


--DATA[8] is DATA[8] at LC_X34_Y16_N5
--operation mode is normal

DATA[8]_lut_out = DIN[0];
DATA[8] = DFFEA(DATA[8]_lut_out, GLOBAL(CLOCK3), VCC, , , , );


--DATA[7] is DATA[7] at LC_X34_Y15_N2
--operation mode is normal

DATA[7]_sload_eqn = DIN[3];
DATA[7] = DFFEA(DATA[7]_sload_eqn, GLOBAL(CLOCK2), VCC, , , , );


--DATA[6] is DATA[6] at LC_X33_Y15_N2
--operation mode is normal

DATA[6]_lut_out = DIN[2];
DATA[6] = DFFEA(DATA[6]_lut_out, GLOBAL(CLOCK2), VCC, , , , );


--DATA[5] is DATA[5] at LC_X34_Y15_N5
--operation mode is normal

DATA[5]_sload_eqn = DIN[1];
DATA[5] = DFFEA(DATA[5]_sload_eqn, GLOBAL(CLOCK2), VCC, , , , );


--DATA[4] is DATA[4] at LC_X34_Y14_N4
--operation mode is normal

DATA[4]_sload_eqn = DIN[0];
DATA[4] = DFFEA(DATA[4]_sload_eqn, GLOBAL(CLOCK2), VCC, , , , );


--DATA[3] is DATA[3] at LC_X34_Y15_N6
--operation mode is normal

DATA[3]_sload_eqn = DIN[3];
DATA[3] = DFFEA(DATA[3]_sload_eqn, GLOBAL(CLOCK1), VCC, , , , );


--DATA[2] is DATA[2] at LC_X33_Y15_N4
--operation mode is normal

DATA[2]_lut_out = DIN[2];
DATA[2] = DFFEA(DATA[2]_lut_out, GLOBAL(CLOCK1), VCC, , , , );


--DATA[1] is DATA[1] at LC_X34_Y15_N4
--operation mode is normal

DATA[1]_sload_eqn = DIN[1];
DATA[1] = DFFEA(DATA[1]_sload_eqn, GLOBAL(CLOCK1), VCC, , , , );


--DATA[0] is DATA[0] at LC_X34_Y14_N8
--operation mode is normal

DATA[0]_sload_eqn = DIN[0];
DATA[0] = DFFEA(DATA[0]_sload_eqn, GLOBAL(CLOCK1), VCC, , , , );


--C1_DOUT[19] is REG32B:U2|DOUT[19] at LC_X27_Y19_N2
--operation mode is normal

C1_DOUT[19]_lut_out = F5_safe_q[3];
C1_DOUT[19] = DFFEA(C1_DOUT[19]_lut_out, !GLOBAL(B1_Div2CLK), VCC, , , , );


--A1L36 is Mux~130 at LC_X27_Y15_N1
--operation mode is normal

C1_DOUT[27]_qfbk = C1_DOUT[27];
A1L36 = SEL[1] & (SEL[0] # C1_DOUT[27]_qfbk) # !SEL[1] & !SEL[0] & C1_DOUT[19];

--C1_DOUT[27] is REG32B:U2|DOUT[27] at LC_X27_Y15_N1
--operation mode is normal

C1_DOUT[27]_sload_eqn = F7_safe_q[3];
C1_DOUT[27] = DFFEA(C1_DOUT[27]_sload_eqn, !GLOBAL(B1_Div2CLK), VCC, , , , );


--C1_DOUT[31] is REG32B:U2|DOUT[31] at LC_X26_Y15_N9
--operation mode is normal

C1_DOUT[31]_lut_out = F8_safe_q[3];
C1_DOUT[31] = DFFEA(C1_DOUT[31]_lut_out, !GLOBAL(B1_Div2CLK), VCC, , , , );


--A1L46 is Mux~131 at LC_X27_Y15_N6
--operation mode is normal

C1_DOUT[23]_qfbk = C1_DOUT[23];
A1L46 = A1L36 & (C1_DOUT[31] # !SEL[0]) # !A1L36 & SEL[0] & C1_DOUT[23]_qfbk;

--C1_DOUT[23] is REG32B:U2|DOUT[23] at LC_X27_Y15_N6
--operation mode is normal

C1_DOUT[23]_sload_eqn = F6_safe_q[3];
C1_DOUT[23] = DFFEA(C1_DOUT[23]_sload_eqn, !GLOBAL(B1_Div2CLK), VCC, , , , );


--C1_DOUT[3] is REG32B:U2|DOUT[3] at LC_X27_Y13_N9
--operation mode is normal

C1_DOUT[3]_lut_out = F1_safe_q[3];
C1_DOUT[3] = DFFEA(C1_DOUT[3]_lut_out, !GLOBAL(B1_Div2CLK), VCC, , , , );


--A1L16 is Mux~128 at LC_X28_Y15_N4
--operation mode is normal

C1_DOUT[7]_qfbk = C1_DOUT[7];
A1L16 = SEL[0] & (SEL[1] # C1_DOUT[7]_qfbk) # !SEL[0] & !SEL[1] & C1_DOUT[3];

--C1_DOUT[7] is REG32B:U2|DOUT[7] at LC_X28_Y15_N4
--operation mode is normal

C1_DOUT[7]_sload_eqn = F2_safe_q[3];
C1_DOUT[7] = DFFEA(C1_DOUT[7]_sload_eqn, !GLOBAL(B1_Div2CLK), VCC, , , , );


--C1_DOUT[15] is REG32B:U2|DOUT[15] at LC_X27_Y16_N6
--operation mode is normal

C1_DOUT[15]_lut_out = F4_safe_q[3];
C1_DOUT[15] = DFFEA(C1_DOUT[15]_lut_out, !GLOBAL(B1_Div2CLK), VCC, , , , );


--A1L26 is Mux~129 at LC_X27_Y15_N9
--operation mode is normal

C1_DOUT[11]_qfbk = C1_DOUT[11];
A1L26 = A1L16 & (C1_DOUT[15] # !SEL[1]) # !A1L16 & SEL[1] & C1_DOUT[11]_qfbk;

--C1_DOUT[11] is REG32B:U2|DOUT[11] at LC_X27_Y15_N9
--operation mode is normal

C1_DOUT[11]_sload_eqn = F3_safe_q[3];
C1_DOUT[11] = DFFEA(C1_DOUT[11]_sload_eqn, !GLOBAL(B1_Div2CLK), VCC, , , , );


--A1L05 is DLOW[3]$latch~66 at LC_X27_Y15_N8
--operation mode is normal

A1L05 = SEL[2] & A1L46 # !SEL[2] & A1L26;


--A1L25 is DLOW[3]$latch~70 at LC_X27_Y15_N3
--operation mode is normal

A1L25 = LCELL(SEL[3] & A1L25 # !SEL[3] & A1L05);


--C1_DOUT[18] is REG32B:U2|DOUT[18] at LC_X27_Y19_N1
--operation mode is normal

C1_DOUT[18]_lut_out = F5_safe_q[2];
C1_DOUT[18] = DFFEA(C1_DOUT[18]_lut_out, !GLOBAL(B1_Div2CLK), VCC, , , , );


--A1L76 is Mux~134 at LC_X27_Y17_N7
--operation mode is normal

C1_DOUT[26]_qfbk = C1_DOUT[26];
A1L76 = SEL[1] & (C1_DOUT[26]_qfbk # SEL[0]) # !SEL[1] & C1_DOUT[18] & !SEL[0];

--C1_DOUT[26] is REG32B:U2|DOUT[26] at LC_X27_Y17_N7
--operation mode is normal

C1_DOUT[26]_sload_eqn = F7_safe_q[2];
C1_DOUT[26] = DFFEA(C1_DOUT[26]_sload_eqn, !GLOBAL(B1_Div2CLK), VCC, , , , );


--C1_DOUT[30] is REG32B:U2|DOUT[30] at LC_X26_Y15_N2
--operation mode is normal

C1_DOUT[30]_lut_out = F8_safe_q[2];
C1_DOUT[30] = DFFEA(C1_DOUT[30]_lut_out, !GLOBAL(B1_Div2CLK), VCC, , , , );


--A1L86 is Mux~135 at LC_X27_Y17_N8
--operation mode is normal

C1_DOUT[22]_qfbk = C1_DOUT[22];
A1L86 = A1L76 & (C1_DOUT[30] # !SEL[0]) # !A1L76 & SEL[0] & C1_DOUT[22]_qfbk;

--C1_DOUT[22] is REG32B:U2|DOUT[22] at LC_X27_Y17_N8
--operation mode is normal

C1_DOUT[22]_sload_eqn = F6_safe_q[2];
C1_DOUT[22] = DFFEA(C1_DOUT[22]_sload_eqn, !GLOBAL(B1_Div2CLK), VCC, , , , );


--C1_DOUT[2] is REG32B:U2|DOUT[2] at LC_X27_Y13_N0
--operation mode is normal

C1_DOUT[2]_lut_out = F1_safe_q[2];
C1_DOUT[2] = DFFEA(C1_DOUT[2]_lut_out, !GLOBAL(B1_Div2CLK), VCC, , , , );


--A1L56 is Mux~132 at LC_X28_Y15_N5
--operation mode is normal

C1_DOUT[6]_qfbk = C1_DOUT[6];
A1L56 = SEL[0] & (SEL[1] # C1_DOUT[6]_qfbk) # !SEL[0] & !SEL[1] & C1_DOUT[2];

--C1_DOUT[6] is REG32B:U2|DOUT[6] at LC_X28_Y15_N5
--operation mode is normal

C1_DOUT[6]_sload_eqn = F2_safe_q[2];
C1_DOUT[6] = DFFEA(C1_DOUT[6]_sload_eqn, !GLOBAL(B1_Div2CLK), VCC, , , , );


--C1_DOUT[14] is REG32B:U2|DOUT[14] at LC_X27_Y16_N7
--operation mode is normal

C1_DOUT[14]_lut_out = F4_safe_q[2];
C1_DOUT[14] = DFFEA(C1_DOUT[14]_lut_out, !GLOBAL(B1_Div2CLK), VCC, , , , );


--A1L66 is Mux~133 at LC_X27_Y17_N5
--operation mode is normal

C1_DOUT[10]_qfbk = C1_DOUT[10];
A1L66 = A1L56 & (C1_DOUT[14] # !SEL[1]) # !A1L56 & SEL[1] & C1_DOUT[10]_qfbk;

--C1_DOUT[10] is REG32B:U2|DOUT[10] at LC_X27_Y17_N5
--operation mode is normal

C1_DOUT[10]_sload_eqn = F3_safe_q[2];
C1_DOUT[10] = DFFEA(C1_DOUT[10]_sload_eqn, !GLOBAL(B1_Div2CLK), VCC, , , , );


--A1L64 is DLOW[2]$latch~64 at LC_X27_Y17_N6
--operation mode is normal

A1L64 = A1L86 & (SEL[2] # A1L66) # !A1L86 & !SEL[2] & A1L66;


--A1L84 is DLOW[2]$latch~66 at LC_X27_Y17_N1
--operation mode is normal

A1L84 = LCELL(A1L64 & (A1L84 # !SEL[3]) # !A1L64 & SEL[3] & A1L84);


--C1_DOUT[17] is REG32B:U2|DOUT[17] at LC_X27_Y19_N5
--operation mode is normal

C1_DOUT[17]_lut_out = F5_safe_q[1];
C1_DOUT[17] = DFFEA(C1_DOUT[17]_lut_out, !GLOBAL(B1_Div2CLK), VCC, , , , );


--A1L17 is Mux~138 at LC_X27_Y17_N4
--operation mode is normal

C1_DOUT[25]_qfbk = C1_DOUT[25];
A1L17 = SEL[1] & (C1_DOUT[25]_qfbk # SEL[0]) # !SEL[1] & C1_DOUT[17] & !SEL[0];

--C1_DOUT[25] is REG32B:U2|DOUT[25] at LC_X27_Y17_N4
--operation mode is normal

C1_DOUT[25]_sload_eqn = F7_safe_q[1];
C1_DOUT[25] = DFFEA(C1_DOUT[25]_sload_eqn, !GLOBAL(B1_Div2CLK), VCC, , , , );


--C1_DOUT[29] is REG32B:U2|DOUT[29] at LC_X26_Y15_N3
--operation mode is normal

C1_DOUT[29]_lut_out = F8_safe_q[1];
C1_DOUT[29] = DFFEA(C1_DOUT[29]_lut_out, !GLOBAL(B1_Div2CLK), VCC, , , , );


--A1L27 is Mux~139 at LC_X26_Y17_N2
--operation mode is normal

C1_DOUT[21]_qfbk = C1_DOUT[21];
A1L27 = A1L17 & (C1_DOUT[29] # !SEL[0]) # !A1L17 & SEL[0] & C1_DOUT[21]_qfbk;

--C1_DOUT[21] is REG32B:U2|DOUT[21] at LC_X26_Y17_N2
--operation mode is normal

C1_DOUT[21]_sload_eqn = F6_safe_q[1];
C1_DOUT[21] = DFFEA(C1_DOUT[21]_sload_eqn, !GLOBAL(B1_Div2CLK), VCC, , , , );


--C1_DOUT[1] is REG32B:U2|DOUT[1] at LC_X27_Y13_N2
--operation mode is normal

C1_DOUT[1]_lut_out = F1_safe_q[1];
C1_DOUT[1] = DFFEA(C1_DOUT[1]_lut_out, !GLOBAL(B1_Div2CLK), VCC, , , , );


--A1L96 is Mux~136 at LC_X26_Y14_N3
--operation mode is normal

C1_DOUT[5]_qfbk = C1_DOUT[5];
A1L96 = SEL[0] & (C1_DOUT[5]_qfbk # SEL[1]) # !SEL[0] & C1_DOUT[1] & !SEL[1];

--C1_DOUT[5] is REG32B:U2|DOUT[5] at LC_X26_Y14_N3
--operation mode is normal

C1_DOUT[5]_sload_eqn = F2_safe_q[1];
C1_DOUT[5] = DFFEA(C1_DOUT[5]_sload_eqn, !GLOBAL(B1_Div2CLK), VCC, , , , );


--C1_DOUT[13] is REG32B:U2|DOUT[13] at LC_X27_Y16_N9
--operation mode is normal

C1_DOUT[13]_lut_out = F4_safe_q[1];
C1_DOUT[13] = DFFEA(C1_DOUT[13]_lut_out, !GLOBAL(B1_Div2CLK), VCC, , , , );


--A1L07 is Mux~137 at LC_X26_Y14_N4
--operation mode is normal

C1_DOUT[9]_qfbk = C1_DOUT[9];
A1L07 = A1L96 & (C1_DOUT[13] # !SEL[1]) # !A1L96 & SEL[1] & C1_DOUT[9]_qfbk;

--C1_DOUT[9] is REG32B:U2|DOUT[9] at LC_X26_Y14_N4
--operation mode is normal

C1_DOUT[9]_sload_eqn = F3_safe_q[1];
C1_DOUT[9] = DFFEA(C1_DOUT[9]_sload_eqn, !GLOBAL(B1_Div2CLK), VCC, , , , );


--A1L24 is DLOW[1]$latch~64 at LC_X26_Y17_N4
--operation mode is normal

A1L24 = A1L27 & (A1L07 # SEL[2]) # !A1L27 & A1L07 & !SEL[2];


--A1L44 is DLOW[1]$latch~66 at LC_X27_Y17_N9
--operation mode is normal

A1L44 = LCELL(A1L44 & (A1L24 # SEL[3]) # !A1L44 & A1L24 & !SEL[3]);


--C1_DOUT[16] is REG32B:U2|DOUT[16] at LC_X27_Y18_N2
--operation mode is normal

C1_DOUT[16]_sload_eqn = F5_safe_q[0];
C1_DOUT[16] = DFFEA(C1_DOUT[16]_sload_eqn, !GLOBAL(B1_Div2CLK), VCC, , , , );


--A1L57 is Mux~142 at LC_X27_Y15_N0
--operation mode is normal

C1_DOUT[24]_qfbk = C1_DOUT[24];
A1L57 = SEL[1] & (SEL[0] # C1_DOUT[24]_qfbk) # !SEL[1] & !SEL[0] & C1_DOUT[16];

--C1_DOUT[24] is REG32B:U2|DOUT[24] at LC_X27_Y15_N0
--operation mode is normal

C1_DOUT[24]_sload_eqn = F7_safe_q[0];
C1_DOUT[24] = DFFEA(C1_DOUT[24]_sload_eqn, !GLOBAL(B1_Div2CLK), VCC, , , , );


--C1_DOUT[28] is REG32B:U2|DOUT[28] at LC_X26_Y15_N4
--operation mode is normal

C1_DOUT[28]_lut_out = F8_safe_q[0];
C1_DOUT[28] = DFFEA(C1_DOUT[28]_lut_out, !GLOBAL(B1_Div2CLK), VCC, , , , );


--A1L67 is Mux~143 at LC_X27_Y15_N4
--operation mode is normal

C1_DOUT[20]_qfbk = C1_DOUT[20];
A1L67 = A1L57 & (C1_DOUT[28] # !SEL[0]) # !A1L57 & SEL[0] & C1_DOUT[20]_qfbk;

--C1_DOUT[20] is REG32B:U2|DOUT[20] at LC_X27_Y15_N4
--operation mode is normal

C1_DOUT[20]_sload_eqn = F6_safe_q[0];
C1_DOUT[20] = DFFEA(C1_DOUT[20]_sload_eqn, !GLOBAL(B1_Div2CLK), VCC, , , , );


--C1_DOUT[0] is REG32B:U2|DOUT[0] at LC_X27_Y13_N3
--operation mode is normal

C1_DOUT[0]_lut_out = F1_safe_q[0];
C1_DOUT[0] = DFFEA(C1_DOUT[0]_lut_out, !GLOBAL(B1_Div2CLK), VCC, , , , );


--A1L37 is Mux~140 at LC_X28_Y15_N1
--operation mode is normal

C1_DOUT[4]_qfbk = C1_DOUT[4];
A1L37 = SEL[0] & (SEL[1] # C1_DOUT[4]_qfbk) # !SEL[0] & !SEL[1] & C1_DOUT[0];

--C1_DOUT[4] is REG32B:U2|DOUT[4] at LC_X28_Y15_N1
--operation mode is normal

C1_DOUT[4]_sload_eqn = F2_safe_q[0];
C1_DOUT[4] = DFFEA(C1_DOUT[4]_sload_eqn, !GLOBAL(B1_Div2CLK), VCC, , , , );


--C1_DOUT[12] is REG32B:U2|DOUT[12] at LC_X27_Y16_N8
--operation mode is normal

C1_DOUT[12]_lut_out = F4_safe_q[0];
C1_DOUT[12] = DFFEA(C1_DOUT[12]_lut_out, !GLOBAL(B1_Div2CLK), VCC, , , , );


--A1L47 is Mux~141 at LC_X27_Y15_N7
--operation mode is normal

C1_DOUT[8]_qfbk = C1_DOUT[8];
A1L47 = A1L37 & (C1_DOUT[12] # !SEL[1]) # !A1L37 & SEL[1] & C1_DOUT[8]_qfbk;

--C1_DOUT[8] is REG32B:U2|DOUT[8] at LC_X27_Y15_N7
--operation mode is normal

C1_DOUT[8]_sload_eqn = F3_safe_q[0];
C1_DOUT[8] = DFFEA(C1_DOUT[8]_sload_eqn, !GLOBAL(B1_Div2CLK), VCC, , , , );