freqtest.tan.summary

基于fpga和sopc的用VHDL语言编写的EDA频率测试与FPGA单片机通讯

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : -0.571 ns
From           : DIN[0]
To             : DATA[8]
From Clock     : 
To Clock       : P37
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 17.048 ns
From           : REG32B:U2|DOUT[17]
To             : DLOW[1]
From Clock     : CLK
To Clock       : 
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 16.279 ns
From           : SEL[0]
To             : DLOW[1]
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 4.192 ns
From           : DIN[2]
To             : DATA[2]
From Clock     : 
To Clock       : SEL[2]
Failed Paths   : 0

Type           : Worst-case Minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 11.700 ns
From           : DATA[5]
To             : DATAOUT[5]
From Clock     : P37
To Clock       : 
Failed Paths   : 0

Type           : Worst-case Minimum tpd
Slack          : N/A
Required Time  : None
Actual Time    : 12.156 ns
From           : SEL[3]
To             : DLOW[1]
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'FSIN'
Slack          : N/A
Required Time  : None
Actual Time    : 157.85 MHz ( period = 6.335 ns )
From           : CNT10:U10|lpm_counter:CQI_rtl_0|cntr_ed8:auto_generated|safe_q[1]
To             : CNT10:U10|lpm_counter:CQI_rtl_0|cntr_ed8:auto_generated|safe_q[3]
From Clock     : FSIN
To Clock       : FSIN
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : TESTCTL:U1|Div2CLK
To             : TESTCTL:U1|Div2CLK
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Hold: 'FSIN'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : CNT10:U10|lpm_counter:CQI_rtl_0|cntr_ed8:auto_generated|safe_q[0]
To             : CNT10:U10|lpm_counter:CQI_rtl_0|cntr_ed8:auto_generated|safe_q[0]
From Clock     : FSIN
To Clock       : FSIN
Failed Paths   : 46

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 46

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