maxplusii_to_quartus_name_mapping.txt

基于fpga和sopc的用VHDL语言编写的EDA频率测试与FPGA单片机通讯

 -- Copyright (C) 1991-2004 Altera Corporation
 -- Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
 -- support information,  device programming or simulation file,  and any other
 -- associated  documentation or information  provided by  Altera  or a partner
 -- under  Altera's   Megafunction   Partnership   Program  may  be  used  only
 -- to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
 -- other  use  of such  megafunction  design,  netlist,  support  information,
 -- device programming or simulation file,  or any other  related documentation
 -- or information  is prohibited  for  any  other purpose,  including, but not
 -- limited to  modification,  reverse engineering,  de-compiling, or use  with
 -- any other  silicon devices,  unless such use is  explicitly  licensed under
 -- a separate agreement with  Altera  or a megafunction partner.  Title to the
 -- intellectual property,  including patents,  copyrights,  trademarks,  trade
 -- secrets,  or maskworks,  embodied in any such megafunction design, netlist,
 -- support  information,  device programming or simulation file,  or any other
 -- related documentation or information provided by  Altera  or a megafunction
 -- partner, remains with Altera, the megafunction partner, or their respective
 -- licensors. No other licenses, including any licenses needed under any third
 -- party's intellectual property, are provided herein.

 -- VERSION "Version 4.1 Build 181 06/29/2004 SJ Full Version"
 -- DATE "09/12/2004 06:59:02"

Conversion results for freqtest
+-----------------------+----------------------+
| MAX+PLUS II node name | Quartus II node name |
+-----------------------+----------------------+
| |DATAOUT0             | DATAOUT[0]           |
| |DATAOUT1             | DATAOUT[1]           |
| |DATAOUT2             | DATAOUT[2]           |
| |DATAOUT3             | DATAOUT[3]           |
| |DATAOUT4             | DATAOUT[4]           |
| |DATAOUT5             | DATAOUT[5]           |
| |DATAOUT6             | DATAOUT[6]           |
| |DATAOUT7             | DATAOUT[7]           |
| |DATAOUT8             | DATAOUT[8]           |
| |DATAOUT9             | DATAOUT[9]           |
| |DATAOUT10            | DATAOUT[10]          |
| |DATAOUT11            | DATAOUT[11]          |
| |DIN0                 | DIN[0]               |
| |DIN1                 | DIN[1]               |
| |DIN2                 | DIN[2]               |
| |DIN3                 | DIN[3]               |
| |DLOW0                | DLOW[0]              |
| |DLOW1                | DLOW[1]              |
| |DLOW2                | DLOW[2]              |
| |DLOW3                | DLOW[3]              |
| |P37                  | P[37]                |
| |SEL0                 | SEL[0]               |
| |SEL1                 | SEL[1]               |
| |SEL2                 | SEL[2]               |
| |SEL3                 | SEL[3]               |
+-----------------------+----------------------+