📄 freqtest.map.rpt
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FREQTEST
|-- TESTCTL:U1
|-- REG32B:U2
|-- CNT10:U3
|-- lpm_counter:CQI_rtl_7
|-- cntr_ed8:auto_generated
|-- CNT10:U4
|-- lpm_counter:CQI_rtl_6
|-- cntr_ed8:auto_generated
|-- CNT10:U5
|-- lpm_counter:CQI_rtl_5
|-- cntr_ed8:auto_generated
|-- CNT10:U6
|-- lpm_counter:CQI_rtl_4
|-- cntr_ed8:auto_generated
|-- CNT10:U7
|-- lpm_counter:CQI_rtl_3
|-- cntr_ed8:auto_generated
|-- CNT10:U8
|-- lpm_counter:CQI_rtl_2
|-- cntr_ed8:auto_generated
|-- CNT10:U9
|-- lpm_counter:CQI_rtl_1
|-- cntr_ed8:auto_generated
|-- CNT10:U10
|-- lpm_counter:CQI_rtl_0
|-- cntr_ed8:auto_generated
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------------------------------------------+
; |FREQTEST ; 125 (44) ; 77 ; 0 ; 27 ; 0 ; 48 (32) ; 45 (12) ; 32 (0) ; 32 (0) ; |FREQTEST ;
; |CNT10:U10| ; 5 (1) ; 4 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (0) ; 4 (0) ; |FREQTEST|CNT10:U10 ;
; |lpm_counter:CQI_rtl_0| ; 4 (0) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (0) ; 4 (0) ; |FREQTEST|CNT10:U10|lpm_counter:CQI_rtl_0 ;
; |cntr_ed8:auto_generated| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 4 (4) ; |FREQTEST|CNT10:U10|lpm_counter:CQI_rtl_0|cntr_ed8:auto_generated ;
; |CNT10:U3| ; 6 (2) ; 4 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 4 (0) ; 4 (0) ; |FREQTEST|CNT10:U3 ;
; |lpm_counter:CQI_rtl_7| ; 4 (0) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (0) ; 4 (0) ; |FREQTEST|CNT10:U3|lpm_counter:CQI_rtl_7 ;
; |cntr_ed8:auto_generated| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 4 (4) ; |FREQTEST|CNT10:U3|lpm_counter:CQI_rtl_7|cntr_ed8:auto_generated ;
; |CNT10:U4| ; 6 (2) ; 4 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 4 (0) ; 4 (0) ; |FREQTEST|CNT10:U4 ;
; |lpm_counter:CQI_rtl_6| ; 4 (0) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (0) ; 4 (0) ; |FREQTEST|CNT10:U4|lpm_counter:CQI_rtl_6 ;
; |cntr_ed8:auto_generated| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 4 (4) ; |FREQTEST|CNT10:U4|lpm_counter:CQI_rtl_6|cntr_ed8:auto_generated ;
; |CNT10:U5| ; 6 (2) ; 4 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 4 (0) ; 4 (0) ; |FREQTEST|CNT10:U5 ;
; |lpm_counter:CQI_rtl_5| ; 4 (0) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (0) ; 4 (0) ; |FREQTEST|CNT10:U5|lpm_counter:CQI_rtl_5 ;
; |cntr_ed8:auto_generated| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 4 (4) ; |FREQTEST|CNT10:U5|lpm_counter:CQI_rtl_5|cntr_ed8:auto_generated ;
; |CNT10:U6| ; 6 (2) ; 4 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 4 (0) ; 4 (0) ; |FREQTEST|CNT10:U6 ;
; |lpm_counter:CQI_rtl_4| ; 4 (0) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (0) ; 4 (0) ; |FREQTEST|CNT10:U6|lpm_counter:CQI_rtl_4 ;
; |cntr_ed8:auto_generated| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 4 (4) ; |FREQTEST|CNT10:U6|lpm_counter:CQI_rtl_4|cntr_ed8:auto_generated ;
; |CNT10:U7| ; 6 (2) ; 4 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 4 (0) ; 4 (0) ; |FREQTEST|CNT10:U7 ;
; |lpm_counter:CQI_rtl_3| ; 4 (0) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (0) ; 4 (0) ; |FREQTEST|CNT10:U7|lpm_counter:CQI_rtl_3 ;
; |cntr_ed8:auto_generated| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 4 (4) ; |FREQTEST|CNT10:U7|lpm_counter:CQI_rtl_3|cntr_ed8:auto_generated ;
; |CNT10:U8| ; 6 (2) ; 4 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 4 (0) ; 4 (0) ; |FREQTEST|CNT10:U8 ;
; |lpm_counter:CQI_rtl_2| ; 4 (0) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (0) ; 4 (0) ; |FREQTEST|CNT10:U8|lpm_counter:CQI_rtl_2 ;
; |cntr_ed8:auto_generated| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 4 (4) ; |FREQTEST|CNT10:U8|lpm_counter:CQI_rtl_2|cntr_ed8:auto_generated ;
; |CNT10:U9| ; 6 (2) ; 4 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 4 (0) ; 4 (0) ; |FREQTEST|CNT10:U9 ;
; |lpm_counter:CQI_rtl_1| ; 4 (0) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (0) ; 4 (0) ; |FREQTEST|CNT10:U9|lpm_counter:CQI_rtl_1 ;
; |cntr_ed8:auto_generated| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 4 (4) ; |FREQTEST|CNT10:U9|lpm_counter:CQI_rtl_1|cntr_ed8:auto_generated ;
; |REG32B:U2| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 (0) ; 32 (32) ; 0 (0) ; 0 (0) ; |FREQTEST|REG32B:U2 ;
; |TESTCTL:U1| ; 2 (2) ; 1 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |FREQTEST|TESTCTL:U1 ;
+------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------------------------------------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/EDA_SOPC6_12/Chpt12_Multi/EP1C6_13_7A_Ftest/FREQTEST.map.eqn.
+----------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------------------------------------+-----------------+
; File Name ; Used in Netlist ;
+----------------------------------------------------------------+-----------------+
; cnt10.vhd ; yes ;
; reg32b.vhd ; yes ;
; testctl.vhd ; yes ;
; freqtest.vhd ; yes ;
; d:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf ; yes ;
; d:/altera/quartus41/libraries/megafunctions/lpm_constant.inc ; yes ;
; D:/EDA_SOPC6_12/Chpt12_Multi/EP1C6_13_7A_Ftest/db/cntr_ed8.tdf ; yes ;
+----------------------------------------------------------------+-----------------+
+--------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+--------------------+
; Resource ; Usage ;
+-----------------------------------+--------------------+
; Logic cells ; 125 ;
; Total combinational functions ; 80 ;
; Total 4-input functions ; 35 ;
; Total 3-input functions ; 8 ;
; Total 2-input functions ; 5 ;
; Total 1-input functions ; 32 ;
; Total 0-input functions ; 0 ;
; Combinational cells for routing ; 0 ;
; Total registers ; 77 ;
; Total logic cells in carry chains ; 32 ;
; I/O pins ; 27 ;
; Maximum fan-out node ; TESTCTL:U1|Div2CLK ;
; Maximum fan-out ; 66 ;
; Total fan-out ; 464 ;
; Average fan-out ; 3.05 ;
+-----------------------------------+--------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
Info: Processing started: Tue Aug 02 13:35:20 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off FREQTEST -c FREQTEST
Info: Found 2 design units, including 1 entities, in source file cnt10.vhd
Info: Found design unit 1: CNT10-behav
Info: Found entity 1: CNT10
Info: Found 2 design units, including 1 entities, in source file reg32b.vhd
Info: Found design unit 1: REG32B-behav
Info: Found entity 1: REG32B
Info: Found 2 design units, including 1 entities, in source file testctl.vhd
Info: Found design unit 1: TESTCTL-behav
Info: Found entity 1: TESTCTL
Info: Found 2 design units, including 1 entities, in source file freqtest.vhd
Info: Found design unit 1: FREQTEST-struc
Info: Found entity 1: FREQTEST
Warning: VHDL Process Statement warning at freqtest.vhd(76): signal dout is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at freqtest.vhd(77): signal dout is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at freqtest.vhd(78): signal dout is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at freqtest.vhd(79): signal dout is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at freqtest.vhd(80): signal dout is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at freqtest.vhd(81): signal dout is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at freqtest.vhd(82): signal dout is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at freqtest.vhd(83): signal dout is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at freqtest.vhd(73): signal or variable dlow may not be assigned a new value in every possible path through the Process Statement. Signal or variable dlow holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at freqtest.vhd(73): signal or variable k1 may not be assigned a new value in every possible path through the Process Statement. Signal or variable k1 holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at freqtest.vhd(73): signal or variable k2 may not be assigned a new value in every possible path through the Process Statement. Signal or variable k2 holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at freqtest.vhd(73): signal or variable k3 may not be assigned a new value in every possible path through the Process Statement. Signal or variable k3 holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Ignored 7 buffer(s)
Info: Ignored 7 SOFT buffer(s)
Info: Inferred 8 megafunctions from design logic
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: CNT10:U10|CQI[0]~4
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: CNT10:U9|CQI[0]~4
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: CNT10:U8|CQI[0]~4
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: CNT10:U7|CQI[0]~4
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: CNT10:U6|CQI[0]~4
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: CNT10:U5|CQI[0]~4
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: CNT10:U4|CQI[0]~4
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: CNT10:U3|CQI[0]~4
Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus41/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file db/cntr_ed8.tdf
Info: Found entity 1: cntr_ed8
Info: Implemented 152 device resources after synthesis - the final resource count might be different
Info: Implemented 11 input pins
Info: Implemented 16 output pins
Info: Implemented 125 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings
Info: Processing ended: Tue Aug 02 13:35:31 2005
Info: Elapsed time: 00:00:10
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