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📄 freqtest.srr

📁 基于fpga和sopc的用VHDL语言编写的EDA频率测试与FPGA单片机通讯
💻 SRR
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字号:
KK2_data[4]     S_DFF     Q       KK2_data[4]     3.9         996.1
KK2_data[5]     S_DFF     Q       KK2_data[5]     3.9         996.1
KK2_data[6]     S_DFF     Q       KK2_data[6]     3.9         996.1
KK2_data[7]     S_DFF     Q       KK2_data[7]     3.9         996.1
===================================================================


End Points for Paths with Slack Worse than 998.3 ns : 

                                             Required          
Instance        Type      Pin     Net        Time         Slack
---------------------------------------------------------------
KK2_data[4]     S_DFF     D       DIN[0]     997.8        997.8
KK2_data[5]     S_DFF     D       DIN[1]     997.8        997.8
KK2_data[6]     S_DFF     D       DIN[2]     997.8        997.8
KK2_data[7]     S_DFF     D       DIN[3]     997.8        997.8
===============================================================


A Critical Path with worst case slack = 996.1 ns:  

Instance/Net                Pin            Pin     Arrival     Delta     Fan
Name              Type      Name           Dir     Time        Delay     Out
----------------------------------------------------------------------------
KK2_data[7]       S_DFF     Q              Out                 3.9          
KK2_data[7]       Net                                                    1  
DATAOUT[11:0]     Port      DATAOUT[7]     In      3.9                      
============================================================================


		Detailed Timing Report for  clock : clock3_inferred_clock 
		*******************************************
Requested Period 	  1000.0 ns
Estimated Period 	  3.9 ns
Worst Slack 	 	 996.1 ns

Start Points for Paths with Slack Worse than 998.3 ns : 

                                                    Arrival          
Instance         Type      Pin     Net              Time        Slack
---------------------------------------------------------------------
KK3_data[8]      S_DFF     Q       KK3_data[8]      3.9         996.1
KK3_data[9]      S_DFF     Q       KK3_data[9]      3.9         996.1
KK3_data[10]     S_DFF     Q       KK3_data[10]     3.9         996.1
KK3_data[11]     S_DFF     Q       KK3_data[11]     3.9         996.1
=====================================================================


End Points for Paths with Slack Worse than 998.3 ns : 

                                              Required          
Instance         Type      Pin     Net        Time         Slack
----------------------------------------------------------------
KK3_data[8]      S_DFF     D       DIN[0]     997.8        997.8
KK3_data[9]      S_DFF     D       DIN[1]     997.8        997.8
KK3_data[10]     S_DFF     D       DIN[2]     997.8        997.8
KK3_data[11]     S_DFF     D       DIN[3]     997.8        997.8
================================================================


A Critical Path with worst case slack = 996.1 ns:  

Instance/Net                Pin             Pin     Arrival     Delta     Fan
Name              Type      Name            Dir     Time        Delay     Out
-----------------------------------------------------------------------------
KK3_data[11]      S_DFF     Q               Out                 3.9          
KK3_data[11]      Net                                                     1  
DATAOUT[11:0]     Port      DATAOUT[11]     In      3.9                      
=============================================================================


		Detailed Timing Report for  clock : U1.TSTEN 
		*******************************************
Requested Period 	  1000.0 ns
Estimated Period 	  10.6 ns
Worst Slack 	 	 989.4 ns

Start Points for Paths with Slack Worse than 991.6 ns : 

                                                  Arrival          
Instance        Type      Pin     Net             Time        Slack
-------------------------------------------------------------------
U1.TSTEN        S_DFF     Q       U1.TSTEN        4.0         990.2
U2.DOUT[0]      S_DFF     Q       U2.DOUT[0]      3.9         989.4
U2.DOUT[1]      S_DFF     Q       U2.DOUT[1]      3.9         989.4
U2.DOUT[2]      S_DFF     Q       U2.DOUT[2]      3.9         989.4
U2.DOUT[3]      S_DFF     Q       U2.DOUT[3]      3.9         989.4
U2.DOUT[4]      S_DFF     Q       U2.DOUT[4]      3.9         989.4
U2.DOUT[5]      S_DFF     Q       U2.DOUT[5]      3.9         989.4
U2.DOUT[6]      S_DFF     Q       U2.DOUT[6]      3.9         989.4
U2.DOUT[7]      S_DFF     Q       U2.DOUT[7]      3.9         989.4
U2.DOUT[8]      S_DFF     Q       U2.DOUT[8]      3.9         990.5
U2.DOUT[9]      S_DFF     Q       U2.DOUT[9]      3.9         990.5
U2.DOUT[10]     S_DFF     Q       U2.DOUT[10]     3.9         990.5
U2.DOUT[11]     S_DFF     Q       U2.DOUT[11]     3.9         990.5
U2.DOUT[12]     S_DFF     Q       U2.DOUT[12]     3.9         990.5
U2.DOUT[13]     S_DFF     Q       U2.DOUT[13]     3.9         990.5
U2.DOUT[14]     S_DFF     Q       U2.DOUT[14]     3.9         990.5
U2.DOUT[15]     S_DFF     Q       U2.DOUT[15]     3.9         990.5
U2.DOUT[16]     S_DFF     Q       U2.DOUT[16]     3.9         989.4
U2.DOUT[17]     S_DFF     Q       U2.DOUT[17]     3.9         989.4
U2.DOUT[18]     S_DFF     Q       U2.DOUT[18]     3.9         989.4
U2.DOUT[19]     S_DFF     Q       U2.DOUT[19]     3.9         989.4
U2.DOUT[20]     S_DFF     Q       U2.DOUT[20]     3.9         989.4
U2.DOUT[21]     S_DFF     Q       U2.DOUT[21]     3.9         989.4
U2.DOUT[22]     S_DFF     Q       U2.DOUT[22]     3.9         989.4
U2.DOUT[23]     S_DFF     Q       U2.DOUT[23]     3.9         989.4
U2.DOUT[24]     S_DFF     Q       U2.DOUT[24]     3.9         990.5
U2.DOUT[25]     S_DFF     Q       U2.DOUT[25]     3.9         990.5
U2.DOUT[26]     S_DFF     Q       U2.DOUT[26]     3.9         990.5
U2.DOUT[27]     S_DFF     Q       U2.DOUT[27]     3.9         990.5
U2.DOUT[28]     S_DFF     Q       U2.DOUT[28]     3.9         990.5
U2.DOUT[29]     S_DFF     Q       U2.DOUT[29]     3.9         990.5
U2.DOUT[30]     S_DFF     Q       U2.DOUT[30]     3.9         990.5
U2.DOUT[31]     S_DFF     Q       U2.DOUT[31]     3.9         990.5
===================================================================


No End Points with Slack Worse than 991.6 ns Found


A Critical Path with worst case slack = 989.4 ns:  

Instance/Net               Pin       Pin     Arrival     Delta     Fan
Name             Type      Name      Dir     Time        Delay     Out
----------------------------------------------------------------------
U2.DOUT[23]      S_DFF     Q         Out                 3.9          
U2.DOUT[23]      Net                                               1  
dlow_6_c[3]      S_LUT     I1        In      3.9                      
dlow_6_c[3]      S_LUT     OUT       Out                 2.8          
dlow_6_c[3]      Net                                               1  
dlow_6[3]        S_CAS     CAS       In      6.7                      
dlow_6[3]        S_CAS     OUT       Out                 1.1          
dlow_6[3]        Net                                               1  
dlow_7[3]        S_LUT     I2        In      7.8                      
dlow_7[3]        S_LUT     OUT       Out                 2.8          
dlow_7[3]        Net                                               1  
DLOW[3]          LAT1      DATA0     In      10.6                     
======================================================================


		Detailed Timing Report for  clock : CLK 
		*******************************************
Requested Period 	  1000.0 ns
Estimated Period 	  8.3 ns
Worst Slack 	 	 991.7 ns

No Start Points with slack worse than 993.9 ns Found


End Points for Paths with Slack Worse than 993.9 ns : 

                                            Required          
Instance     Type      Pin     Net          Time         Slack
--------------------------------------------------------------
U1.TSTEN     S_DFF     D       tsten1_i     997.8        991.7
==============================================================


 Cannot Find any complete critical path 

		 ##### END TIMING REPORT #####


---------------------------------------
Resource Usage Report

Synplify is performing all technology mapping
Post place and route resource use may vary a small
amount due to logic cell replication and register packing
decisions during place and route.

Design view:work.FREQTEST(struc)
Selecting part epf10k20tc144-3

@N:"d:\k30demo\sendfre\freqtest.vhd":49:2:49:3|Found black box instance work.FREQTEST(struc)-U3 of view:work.cnt10(black_box) without an altera_area attribute.  Reports will not include any lcells for this instance 
@N:"d:\k30demo\sendfre\freqtest.vhd":51:2:51:3|Found black box instance work.FREQTEST(struc)-U4 of view:work.cnt10(black_box) without an altera_area attribute.  Reports will not include any lcells for this instance 
@N:"d:\k30demo\sendfre\freqtest.vhd":54:2:54:3|Found black box instance work.FREQTEST(struc)-U5 of view:work.cnt10(black_box) without an altera_area attribute.  Reports will not include any lcells for this instance 
@N:"d:\k30demo\sendfre\freqtest.vhd":57:2:57:3|Found black box instance work.FREQTEST(struc)-U6 of view:work.cnt10(black_box) without an altera_area attribute.  Reports will not include any lcells for this instance 
@N:"d:\k30demo\sendfre\freqtest.vhd":60:2:60:3|Found black box instance work.FREQTEST(struc)-U7 of view:work.cnt10(black_box) without an altera_area attribute.  Reports will not include any lcells for this instance 
@N:"d:\k30demo\sendfre\freqtest.vhd":63:2:63:3|Found black box instance work.FREQTEST(struc)-U8 of view:work.cnt10(black_box) without an altera_area attribute.  Reports will not include any lcells for this instance 
@N:"d:\k30demo\sendfre\freqtest.vhd":66:2:66:3|Found black box instance work.FREQTEST(struc)-U9 of view:work.cnt10(black_box) without an altera_area attribute.  Reports will not include any lcells for this instance 
@N:"d:\k30demo\sendfre\freqtest.vhd":69:2:69:4|Found black box instance work.FREQTEST(struc)-U10 of view:work.cnt10(black_box) without an altera_area attribute.  Reports will not include any lcells for this instance 
Logic resources:  74 LCs of 1152 ( 6%)
Number of Nets:   139
Number of Inputs: 368
Register bits:   45
I/O cells:       27

Details:
Cells in logic mode:   22
Cells in arith mode:   0
Cells in cascade mode: 8
Cells in counter mode: 0
DFFs with no logic:    44  (uses cell for routing)
LUTs driving both DFF and logic: 1


Creating updateacf script d:\k30demo\sendfre\freqtest.sat to pass constraints to MAX+plusII
Found clock clock3_inferred_clock with period 1000ns
Found clock clock2_inferred_clock with period 1000ns
Found clock clock1_inferred_clock with period 1000ns
All Constraints processed!
Mapper successful!
Process took 2.91 seconds realtime, 2.91 seconds cputime

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