📄 freqtest.srr
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$ Start of Compile
#Sun Sep 09 01:28:12 2001
Synplify VHDL Compiler, version 5.1.2, built Apr 14 1999
Copyright (C) 1994-1999, Synplicity Inc. All Rights Reserved
VHDL syntax check successful!
Synthesizing work.freqtest.struc
@W:"d:\k30demo\sendfre\freqtest.vhd":23:10:23:14|Unbound component mapped to black box
@W:"d:\k30demo\sendfre\freqtest.vhd":69:2:69:4|Port carry_out of entity work.cnt10 is unconnected
@W:"d:\k30demo\sendfre\freqtest.vhd":72:8:72:14|Incomplete sensitivity list - assuming completeness
@W:"d:\k30demo\sendfre\freqtest.vhd":75:36:75:39|Referenced variable dout is not in sensitivity list
Synthesizing work.cnt10.black_box
Post processing for work.cnt10.black_box
Synthesizing work.reg32b.behav
Post processing for work.reg32b.behav
Synthesizing work.testctl.behav
Post processing for work.testctl.behav
Post processing for work.freqtest.struc
@W:"d:\k30demo\sendfre\freqtest.vhd":74:8:74:11|Latch generated from process for signal k3, probably caused by a missing assignment in an if or case stmt
@W:"d:\k30demo\sendfre\freqtest.vhd":74:8:74:11|Latch generated from process for signal k2, probably caused by a missing assignment in an if or case stmt
@W:"d:\k30demo\sendfre\freqtest.vhd":74:8:74:11|Latch generated from process for signal k1, probably caused by a missing assignment in an if or case stmt
@W:"d:\k30demo\sendfre\freqtest.vhd":74:8:74:11|Latch generated from process for signal dlow(3 downto 0), probably caused by a missing assignment in an if or case stmt
@END
Process took 0.33 seconds realtime, 0.33 seconds cputime
Synplify Altera Technology Mapper, version 5.1.2, built Apr 14 1999
Copyright (C) 1994-1998, Synplicity Inc. All Rights Reserved
Loading timing data for chip EPF10K20-3
List of partitions to map:
view:work.FREQTEST(struc)
Automatic dissolve at startup in view:work.FREQTEST(struc) of U2(REG32B)
Automatic dissolve at startup in view:work.FREQTEST(struc) of U1(TESTCTL)
Loading timing data for chip EPF10K20-3
Found clock clock1_inferred_clock with period 1000ns
Found clock clock2_inferred_clock with period 1000ns
Found clock clock3_inferred_clock with period 1000ns
##### START TIMING REPORT #####
Set the Environment Variable SYNPLIFY_TIMING_REPORT_OLD to get the old timing report
Performance Summary
*********************
Requested Estimated Requested Estimated
Clock Frequency Frequency Period Period Slack
---------------------------------------------------------------------------------------
System 1.0 MHz 149.3 MHz 1000.0 6.7 993.3
clock1_inferred_clock 1.0 MHz 256.4 MHz 1000.0 3.9 996.1
clock2_inferred_clock 1.0 MHz 256.4 MHz 1000.0 3.9 996.1
clock3_inferred_clock 1.0 MHz 256.4 MHz 1000.0 3.9 996.1
U1.TSTEN 1.0 MHz 94.3 MHz 1000.0 10.6 989.4
CLK 1.0 MHz 120.5 MHz 1000.0 8.3 991.7
=======================================================================================
Interface Information
***********************
Input Ports:
Port Reference User Arrival Required
Name Clock Constraint Time Time Slack
-----------------------------------------------------------------------------------
DIN[0] clock1_inferred_clock 0.0 0.0 997.8 997.8
DIN[1] clock1_inferred_clock 0.0 0.0 997.8 997.8
DIN[2] clock1_inferred_clock 0.0 0.0 997.8 997.8
DIN[3] clock1_inferred_clock 0.0 0.0 997.8 997.8
FSIN U1.TSTEN 0.0 0.0 1000.0 1000.0
SEL[0] System 0.0 0.0 993.3 993.3
SEL[1] System 0.0 0.0 993.3 993.3
SEL[2] System 0.0 0.0 996.4 996.4
SEL[3] System 0.0 0.0 995.9 995.9
===================================================================================
Output Ports:
Port Reference User Arrival Required
Name Clock Constraint Time Time Slack
----------------------------------------------------------------------------------------
DATAOUT[0] clock1_inferred_clock 0.0 3.9 1000.0 996.1
DATAOUT[1] clock1_inferred_clock 0.0 3.9 1000.0 996.1
DATAOUT[2] clock1_inferred_clock 0.0 3.9 1000.0 996.1
DATAOUT[3] clock1_inferred_clock 0.0 3.9 1000.0 996.1
DATAOUT[4] clock1_inferred_clock 0.0 3.9 1000.0 996.1
DATAOUT[5] clock1_inferred_clock 0.0 3.9 1000.0 996.1
DATAOUT[6] clock1_inferred_clock 0.0 3.9 1000.0 996.1
DATAOUT[7] clock1_inferred_clock 0.0 3.9 1000.0 996.1
DATAOUT[8] clock1_inferred_clock 0.0 3.9 1000.0 996.1
DATAOUT[9] clock1_inferred_clock 0.0 3.9 1000.0 996.1
DATAOUT[10] clock1_inferred_clock 0.0 3.9 1000.0 996.1
DATAOUT[11] clock1_inferred_clock 0.0 3.9 1000.0 996.1
DLOW[0] U1.TSTEN 0.0 0.0 1000.0 1000.0
DLOW[1] U1.TSTEN 0.0 0.0 1000.0 1000.0
DLOW[2] U1.TSTEN 0.0 0.0 1000.0 1000.0
DLOW[3] U1.TSTEN 0.0 0.0 1000.0 1000.0
========================================================================================
Detailed Timing Report for clock : System
*******************************************
Requested Period 1000.0 ns
Estimated Period 6.7 ns
Worst Slack 993.3 ns
Start Points for Paths with Slack Worse than 995.5 ns :
Arrival
Instance Type Pin Net Time Slack
-------------------------------------------------------------
SEL[3:0] Port SEL[0] SEL[0] 0.0 993.3
SEL[3:0] Port SEL[1] SEL[1] 0.0 993.3
=============================================================
No End Points with Slack Worse than 995.5 ns Found
A Critical Path with worst case slack = 993.3 ns:
Instance/Net Pin Pin Arrival Delta Fan
Name Type Name Dir Time Delay Out
-----------------------------------------------------------------------
SEL[3:0] Port SEL[0] Out 0.0
SEL[0] Net 20
dlow_3_c[0] S_LUT I2 In 0.0
dlow_3_c[0] S_LUT OUT Out 6.7
dlow_3_c[0] Net 1
dlow_3[0] S_CAS CAS In 6.7
dlow_3[0] S_CAS OUT Out 1.1
dlow_3[0] Net 1
dlow_7[0] S_LUT I1 In 7.8
dlow_7[0] S_LUT OUT Out 2.8
dlow_7[0] Net 1
DLOW[0] LAT1 DATA0 In 10.6
=======================================================================
Detailed Timing Report for clock : clock1_inferred_clock
*******************************************
Requested Period 1000.0 ns
Estimated Period 3.9 ns
Worst Slack 996.1 ns
Start Points for Paths with Slack Worse than 998.3 ns :
Arrival
Instance Type Pin Net Time Slack
----------------------------------------------------------------------
DIN[3:0] Port DIN[0] DIN[0] 0.0 997.8
DIN[3:0] Port DIN[1] DIN[1] 0.0 997.8
DIN[3:0] Port DIN[2] DIN[2] 0.0 997.8
DIN[3:0] Port DIN[3] DIN[3] 0.0 997.8
KK1_data[0] S_DFF Q KK1_data[0] 3.9 996.1
KK1_data[1] S_DFF Q KK1_data[1] 3.9 996.1
KK1_data[2] S_DFF Q KK1_data[2] 3.9 996.1
KK1_data[3] S_DFF Q KK1_data[3] 3.9 996.1
======================================================================
End Points for Paths with Slack Worse than 998.3 ns :
Required
Instance Type Pin Net Time Slack
-------------------------------------------------------------------------------
DATAOUT[11:0] Port DATAOUT[0] KK1_data[0] 1000.0 996.1
DATAOUT[11:0] Port DATAOUT[1] KK1_data[1] 1000.0 996.1
DATAOUT[11:0] Port DATAOUT[2] KK1_data[2] 1000.0 996.1
DATAOUT[11:0] Port DATAOUT[3] KK1_data[3] 1000.0 996.1
DATAOUT[11:0] Port DATAOUT[4] KK2_data[4] 1000.0 996.1
DATAOUT[11:0] Port DATAOUT[5] KK2_data[5] 1000.0 996.1
DATAOUT[11:0] Port DATAOUT[6] KK2_data[6] 1000.0 996.1
DATAOUT[11:0] Port DATAOUT[7] KK2_data[7] 1000.0 996.1
DATAOUT[11:0] Port DATAOUT[8] KK3_data[8] 1000.0 996.1
DATAOUT[11:0] Port DATAOUT[9] KK3_data[9] 1000.0 996.1
DATAOUT[11:0] Port DATAOUT[10] KK3_data[10] 1000.0 996.1
DATAOUT[11:0] Port DATAOUT[11] KK3_data[11] 1000.0 996.1
KK1_data[0] S_DFF D DIN[0] 997.8 997.8
KK1_data[1] S_DFF D DIN[1] 997.8 997.8
KK1_data[2] S_DFF D DIN[2] 997.8 997.8
KK1_data[3] S_DFF D DIN[3] 997.8 997.8
===============================================================================
A Critical Path with worst case slack = 996.1 ns:
Instance/Net Pin Pin Arrival Delta Fan
Name Type Name Dir Time Delay Out
----------------------------------------------------------------------------
KK1_data[3] S_DFF Q Out 3.9
KK1_data[3] Net 1
DATAOUT[11:0] Port DATAOUT[3] In 3.9
============================================================================
Detailed Timing Report for clock : clock2_inferred_clock
*******************************************
Requested Period 1000.0 ns
Estimated Period 3.9 ns
Worst Slack 996.1 ns
Start Points for Paths with Slack Worse than 998.3 ns :
Arrival
Instance Type Pin Net Time Slack
-------------------------------------------------------------------
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