📄 freqtest.rpt
字号:
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: f:\xd_dsp\disk5\pk-1k30\sendfreok\freqtest.rpt
freqtest
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A5 6/ 8( 75%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 8/22( 36%)
A6 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 2/22( 9%)
A8 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 2/2 1/2 2/22( 9%)
A9 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 2/22( 9%)
A10 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 2/2 1/2 3/22( 13%)
A13 6/ 8( 75%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 8/22( 36%)
A15 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 2/2 1/2 3/22( 13%)
A18 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 2/2 1/2 7/22( 31%)
A21 2/ 8( 25%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 4/22( 18%)
B7 6/ 8( 75%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 12/22( 54%)
B9 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 12/22( 54%)
B11 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 2/2 1/2 5/22( 22%)
B14 7/ 8( 87%) 2/ 8( 25%) 3/ 8( 37%) 2/2 1/2 3/22( 13%)
B15 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B16 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 1/2 3/22( 13%)
B17 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 1/2 3/22( 13%)
B20 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 0/22( 0%)
C1 3/ 8( 37%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 4/22( 18%)
C2 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 12/22( 54%)
C3 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/22( 9%)
C4 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
C6 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
C7 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 1/2 0/2 13/22( 59%)
C9 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
C12 3/ 8( 37%) 3/ 8( 37%) 3/ 8( 37%) 0/2 0/2 4/22( 18%)
C13 5/ 8( 62%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 8/22( 36%)
C14 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
C15 6/ 8( 75%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 8/22( 36%)
C18 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
C19 2/ 8( 25%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 4/22( 18%)
D3 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
D4 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
D18 3/ 8( 37%) 0/ 8( 0%) 3/ 8( 37%) 2/2 0/2 5/22( 22%)
E1 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
E10 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
E15 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
F2 3/ 8( 37%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 4/22( 18%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 2/6 ( 33%)
Total I/O pins used: 25/96 ( 26%)
Total logic cells used: 155/1728 ( 8%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 2.56/4 ( 64%)
Total fan-in: 398/6912 ( 5%)
Total input pins required: 11
Total input I/O cell registers required: 0
Total output pins required: 16
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 155
Total flipflops required: 77
Total packed registers required: 0
Total logic cells in carry chains: 32
Total number of carry chains: 8
Total number of carry chains of length 1-8 : 8
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 0/1728 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 6 1 0 8 1 8 0 0 6 0 8 0 0 8 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48/0
B: 0 0 0 0 0 0 6 0 8 0 8 0 0 7 1 8 8 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 47/0
C: 3 8 1 1 0 8 8 0 1 0 0 3 5 1 6 0 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48/0
D: 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5/0
E: 1 0 0 0 0 0 0 0 0 1 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4/0
F: 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3/0
Total: 4 11 2 2 6 9 14 8 10 9 8 3 11 8 17 8 8 12 0 2 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 155/0
Device-Specific Information: f:\xd_dsp\disk5\pk-1k30\sendfreok\freqtest.rpt
freqtest
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
54 - - - -- INPUT G ^ 0 0 0 1 CLK
114 - - - 06 INPUT ^ 0 0 0 3 DIN0
113 - - - 05 INPUT ^ 0 0 0 3 DIN1
112 - - - 04 INPUT ^ 0 0 0 3 DIN2
111 - - - 03 INPUT ^ 0 0 0 3 DIN3
126 - - - -- INPUT G ^ 0 0 0 0 FSIN
144 - - - 36 INPUT ^ 0 0 0 3 P37
11 - - C -- INPUT ^ 0 0 0 11 SEL0
109 - - - 01 INPUT ^ 0 0 0 11 SEL1
110 - - - 02 INPUT ^ 0 0 0 11 SEL2
14 - - C -- INPUT ^ 0 0 0 11 SEL3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\xd_dsp\disk5\pk-1k30\sendfreok\freqtest.rpt
freqtest
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
81 - - F -- OUTPUT 0 1 0 0 DATAOUT0
82 - - F -- OUTPUT 0 1 0 0 DATAOUT1
83 - - E -- OUTPUT 0 1 0 0 DATAOUT2
86 - - E -- OUTPUT 0 1 0 0 DATAOUT3
87 - - E -- OUTPUT 0 1 0 0 DATAOUT4
88 - - D -- OUTPUT 0 1 0 0 DATAOUT5
89 - - D -- OUTPUT 0 1 0 0 DATAOUT6
90 - - D -- OUTPUT 0 1 0 0 DATAOUT7
91 - - D -- OUTPUT 0 1 0 0 DATAOUT8
92 - - D -- OUTPUT 0 1 0 0 DATAOUT9
95 - - C -- OUTPUT 0 1 0 0 DATAOUT10
96 - - C -- OUTPUT 0 1 0 0 DATAOUT11
119 - - - 13 OUTPUT 0 1 0 0 DLOW0
118 - - - 09 OUTPUT 0 1 0 0 DLOW1
117 - - - 08 OUTPUT 0 1 0 0 DLOW2
116 - - - 07 OUTPUT 0 1 0 0 DLOW3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\xd_dsp\disk5\pk-1k30\sendfreok\freqtest.rpt
freqtest
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - A 08 DFFE + 0 3 0 3 |CNT10:U3|CQI3 (|CNT10:U3|:9)
- 4 - A 08 DFFE + 0 3 0 3 |CNT10:U3|CQI2 (|CNT10:U3|:10)
- 3 - A 08 DFFE + 0 3 0 3 |CNT10:U3|CQI1 (|CNT10:U3|:11)
- 2 - A 08 DFFE + 0 3 0 3 |CNT10:U3|CQI0 (|CNT10:U3|:12)
- 8 - A 08 OR2 0 4 0 4 |CNT10:U3|:48
- 1 - A 08 AND2 0 4 0 4 |CNT10:U3|:185
- 5 - B 17 DFFE 0 4 0 3 |CNT10:U4|CQI3 (|CNT10:U4|:9)
- 4 - B 17 DFFE 0 4 0 3 |CNT10:U4|CQI2 (|CNT10:U4|:10)
- 3 - B 17 DFFE 0 4 0 3 |CNT10:U4|CQI1 (|CNT10:U4|:11)
- 2 - B 17 DFFE 0 4 0 3 |CNT10:U4|CQI0 (|CNT10:U4|:12)
- 8 - B 17 OR2 0 4 0 4 |CNT10:U4|:48
- 1 - B 17 AND2 0 4 0 4 |CNT10:U4|:185
- 8 - B 16 DFFE 0 4 0 3 |CNT10:U5|CQI3 (|CNT10:U5|:9)
- 7 - B 16 DFFE 0 4 0 3 |CNT10:U5|CQI2 (|CNT10:U5|:10)
- 6 - B 16 DFFE 0 4 0 3 |CNT10:U5|CQI1 (|CNT10:U5|:11)
- 5 - B 16 DFFE 0 4 0 3 |CNT10:U5|CQI0 (|CNT10:U5|:12)
- 4 - B 16 OR2 0 4 0 4 |CNT10:U5|:48
- 2 - B 16 AND2 0 4 0 4 |CNT10:U5|:185
- 6 - B 14 DFFE 0 4 0 3 |CNT10:U6|CQI3 (|CNT10:U6|:9)
- 5 - B 14 DFFE 0 4 0 3 |CNT10:U6|CQI2 (|CNT10:U6|:10)
- 4 - B 14 DFFE 0 4 0 3 |CNT10:U6|CQI1 (|CNT10:U6|:11)
- 3 - B 14 DFFE 0 4 0 3 |CNT10:U6|CQI0 (|CNT10:U6|:12)
- 7 - B 14 OR2 0 4 0 4 |CNT10:U6|:48
- 1 - B 14 AND2 0 4 0 4 |CNT10:U6|:185
- 5 - B 11 DFFE 0 4 0 3 |CNT10:U7|CQI3 (|CNT10:U7|:9)
- 4 - B 11 DFFE 0 4 0 3 |CNT10:U7|CQI2 (|CNT10:U7|:10)
- 3 - B 11 DFFE 0 4 0 3 |CNT10:U7|CQI1 (|CNT10:U7|:11)
- 2 - B 11 DFFE 0 4 0 3 |CNT10:U7|CQI0 (|CNT10:U7|:12)
- 8 - B 11 OR2 0 4 0 4 |CNT10:U7|:48
- 6 - B 11 AND2 0 4 0 4 |CNT10:U7|:185
- 4 - A 10 DFFE 0 4 0 3 |CNT10:U8|CQI3 (|CNT10:U8|:9)
- 3 - A 10 DFFE 0 4 0 3 |CNT10:U8|CQI2 (|CNT10:U8|:10)
- 2 - A 10 DFFE 0 4 0 3 |CNT10:U8|CQI1 (|CNT10:U8|:11)
- 1 - A 10 DFFE 0 4 0 3 |CNT10:U8|CQI0 (|CNT10:U8|:12)
- 8 - A 10 OR2 0 4 0 4 |CNT10:U8|:48
- 6 - A 10 AND2 0 4 0 4 |CNT10:U8|:185
- 4 - A 15 DFFE 0 4 0 3 |CNT10:U9|CQI3 (|CNT10:U9|:9)
- 3 - A 15 DFFE 0 4 0 3 |CNT10:U9|CQI2 (|CNT10:U9|:10)
- 2 - A 15 DFFE 0 4 0 3 |CNT10:U9|CQI1 (|CNT10:U9|:11)
- 1 - A 15 DFFE 0 4 0 3 |CNT10:U9|CQI0 (|CNT10:U9|:12)
- 8 - A 15 OR2 0 4 0 4 |CNT10:U9|:48
- 7 - A 15 AND2 0 4 0 4 |CNT10:U9|:185
- 4 - A 18 DFFE 0 4 0 2 |CNT10:U10|CQI3 (|CNT10:U10|:9)
- 3 - A 18 DFFE 0 4 0 2 |CNT10:U10|CQI2 (|CNT10:U10|:10)
- 2 - A 18 DFFE 0 4 0 2 |CNT10:U10|CQI1 (|CNT10:U10|:11)
- 1 - A 18 DFFE 0 4 0 2 |CNT10:U10|CQI0 (|CNT10:U10|:12)
- 6 - A 18 OR2 0 4 0 4 |CNT10:U10|:48
- 8 - A 18 DFFE 0 2 0 1 |REG32B:U2|:34
- 2 - A 05 DFFE 0 2 0 1 |REG32B:U2|:36
- 6 - A 13 DFFE 0 2 0 1 |REG32B:U2|:38
- 5 - C 15 DFFE 0 2 0 1 |REG32B:U2|:40
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