📄 freqtest.rpt
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Project Information f:\xd_dsp\disk5\pk-1k30\sendfreok\freqtest.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 09/10/2004 20:37:21
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
FREQTEST
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
freqtest EP1K30TC144-3 11 16 0 0 0 % 155 8 %
User Pins: 11 16 0
Project Information f:\xd_dsp\disk5\pk-1k30\sendfreok\freqtest.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
freqtest@54 CLK
freqtest@81 DATAOUT0
freqtest@82 DATAOUT1
freqtest@83 DATAOUT2
freqtest@86 DATAOUT3
freqtest@87 DATAOUT4
freqtest@88 DATAOUT5
freqtest@89 DATAOUT6
freqtest@90 DATAOUT7
freqtest@91 DATAOUT8
freqtest@92 DATAOUT9
freqtest@95 DATAOUT10
freqtest@96 DATAOUT11
freqtest@114 DIN0
freqtest@113 DIN1
freqtest@112 DIN2
freqtest@111 DIN3
freqtest@119 DLOW0
freqtest@118 DLOW1
freqtest@117 DLOW2
freqtest@116 DLOW3
freqtest@126 FSIN
freqtest@144 P37
freqtest@11 SEL0
freqtest@109 SEL1
freqtest@110 SEL2
freqtest@14 SEL3
Project Information f:\xd_dsp\disk5\pk-1k30\sendfreok\freqtest.rpt
** FILE HIERARCHY **
|testctl:U1|
|reg32b:U2|
|cnt10:U3|
|cnt10:U3|lpm_add_sub:77|
|cnt10:U3|lpm_add_sub:77|addcore:adder|
|cnt10:U3|lpm_add_sub:77|altshift:result_ext_latency_ffs|
|cnt10:U3|lpm_add_sub:77|altshift:carry_ext_latency_ffs|
|cnt10:U3|lpm_add_sub:77|altshift:oflow_ext_latency_ffs|
|cnt10:U4|
|cnt10:U4|lpm_add_sub:77|
|cnt10:U4|lpm_add_sub:77|addcore:adder|
|cnt10:U4|lpm_add_sub:77|altshift:result_ext_latency_ffs|
|cnt10:U4|lpm_add_sub:77|altshift:carry_ext_latency_ffs|
|cnt10:U4|lpm_add_sub:77|altshift:oflow_ext_latency_ffs|
|cnt10:U5|
|cnt10:U5|lpm_add_sub:77|
|cnt10:U5|lpm_add_sub:77|addcore:adder|
|cnt10:U5|lpm_add_sub:77|altshift:result_ext_latency_ffs|
|cnt10:U5|lpm_add_sub:77|altshift:carry_ext_latency_ffs|
|cnt10:U5|lpm_add_sub:77|altshift:oflow_ext_latency_ffs|
|cnt10:U6|
|cnt10:U6|lpm_add_sub:77|
|cnt10:U6|lpm_add_sub:77|addcore:adder|
|cnt10:U6|lpm_add_sub:77|altshift:result_ext_latency_ffs|
|cnt10:U6|lpm_add_sub:77|altshift:carry_ext_latency_ffs|
|cnt10:U6|lpm_add_sub:77|altshift:oflow_ext_latency_ffs|
|cnt10:U7|
|cnt10:U7|lpm_add_sub:77|
|cnt10:U7|lpm_add_sub:77|addcore:adder|
|cnt10:U7|lpm_add_sub:77|altshift:result_ext_latency_ffs|
|cnt10:U7|lpm_add_sub:77|altshift:carry_ext_latency_ffs|
|cnt10:U7|lpm_add_sub:77|altshift:oflow_ext_latency_ffs|
|cnt10:U8|
|cnt10:U8|lpm_add_sub:77|
|cnt10:U8|lpm_add_sub:77|addcore:adder|
|cnt10:U8|lpm_add_sub:77|altshift:result_ext_latency_ffs|
|cnt10:U8|lpm_add_sub:77|altshift:carry_ext_latency_ffs|
|cnt10:U8|lpm_add_sub:77|altshift:oflow_ext_latency_ffs|
|cnt10:U9|
|cnt10:U9|lpm_add_sub:77|
|cnt10:U9|lpm_add_sub:77|addcore:adder|
|cnt10:U9|lpm_add_sub:77|altshift:result_ext_latency_ffs|
|cnt10:U9|lpm_add_sub:77|altshift:carry_ext_latency_ffs|
|cnt10:U9|lpm_add_sub:77|altshift:oflow_ext_latency_ffs|
|cnt10:U10|
|cnt10:U10|lpm_add_sub:77|
|cnt10:U10|lpm_add_sub:77|addcore:adder|
|cnt10:U10|lpm_add_sub:77|altshift:result_ext_latency_ffs|
|cnt10:U10|lpm_add_sub:77|altshift:carry_ext_latency_ffs|
|cnt10:U10|lpm_add_sub:77|altshift:oflow_ext_latency_ffs|
Device-Specific Information: f:\xd_dsp\disk5\pk-1k30\sendfreok\freqtest.rpt
freqtest
***** Logic for device 'freqtest' compiled without errors.
Device: EP1K30TC144-3
ACEX 1K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R R
E E E E E E E E E E E E E E E E
S S S S S S S S S S S S S V S S S
E E E E E E E E V E E E E E C E E E D D D D V
R R R R R R R R C R R R R R C F R R R L L L L C D D D D S S
P V V V V G V V V V C V V V V G V I S G G G V V V O O O O C I I I I E E
3 E E E E N E E E E I E E E E N E N I N N N E E E W W W W I N N N N L L
7 D D D D D D D D D O D D D D D D T N D D D D D D 0 1 2 3 O 0 1 2 3 2 1
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GND
GND | 6 103 | VCCINT
RESERVED | 7 102 | RESERVED
RESERVED | 8 101 | RESERVED
RESERVED | 9 100 | RESERVED
RESERVED | 10 99 | RESERVED
SEL0 | 11 98 | RESERVED
RESERVED | 12 97 | RESERVED
RESERVED | 13 96 | DATAOUT11
SEL3 | 14 95 | DATAOUT10
GND | 15 94 | VCCIO
VCCINT | 16 93 | GND
RESERVED | 17 92 | DATAOUT9
RESERVED | 18 91 | DATAOUT8
RESERVED | 19 EP1K30TC144-3 90 | DATAOUT7
RESERVED | 20 89 | DATAOUT6
RESERVED | 21 88 | DATAOUT5
RESERVED | 22 87 | DATAOUT4
RESERVED | 23 86 | DATAOUT3
VCCIO | 24 85 | VCCINT
GND | 25 84 | GND
RESERVED | 26 83 | DATAOUT2
RESERVED | 27 82 | DATAOUT1
RESERVED | 28 81 | DATAOUT0
RESERVED | 29 80 | RESERVED
RESERVED | 30 79 | RESERVED
RESERVED | 31 78 | RESERVED
RESERVED | 32 77 | ^MSEL0
RESERVED | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
RESERVED | 36 73 | RESERVED
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R R R G R R R R V R R R R V R G V C G G G G R R V R R R R G R R R R V R
E E E N E E E E C E E E E C E N C L N N N N E E C E E E E N E E E E C E
S S S D S S S S C S S S S C S D C K D D D D S S C S S S S D S S S S C S
E E E E E E E I E E E E I E I E E I E E E E E E E E I E
R R R R R R R O R R R R N R N R R O R R R R R R R R O R
V V V V V V V V V V V T V T V V V V V V V V V V V
E E E E E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
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