tennis.map.summary

基于fpga和sopc的用VHDL语言编写的EDA乒乓球游戏电路

Flow Status : Successful - Tue Aug 02 08:18:32 2005
Quartus II Version : 4.1 Build 181 06/29/2004 SJ Full Version
Revision Name : TENNIS
Top-level Entity Name : TENNIS
Family : Cyclone
Device : EP1C6Q240C8
Timing Models : Production
Total logic elements : 45
Total pins : 31
Total memory bits : 0
Total PLLs : 0