multi8x8.map.rpt

基于fpga和sopc的用VHDL语言编写的EDA移位相加硬件乘法器

+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 20    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 5     ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------+
; Hierarchy ;
+-----------+
MULTI8X8
 |-- ARICTL:U1
      |-- lpm_counter:CNT4B_rtl_0
           |-- cntr_qu7:auto_generated
 |-- SREG8B:U2
 |-- ANDARITH:U3
 |-- ADDER8B:U4
      |-- ADDER4B:U1
      |-- ADDER4B:U2
 |-- REG16B:U5


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                               ;
+------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------------------------------------------------------+
; Compilation Hierarchy Node         ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                                                 ;
+------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------------------------------------------------------+
; |MULTI8X8                          ; 39 (1)      ; 28           ; 0           ; 34   ; 0            ; 11 (1)       ; 8 (0)             ; 20 (0)           ; 14 (0)          ; |MULTI8X8                                                           ;
;    |ANDARITH:U3|                   ; 8 (8)       ; 0            ; 0           ; 0    ; 0            ; 8 (8)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |MULTI8X8|ANDARITH:U3                                               ;
;    |ARICTL:U1|                     ; 5 (1)       ; 4            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |MULTI8X8|ARICTL:U1                                                 ;
;       |lpm_counter:CNT4B_rtl_0|    ; 4 (0)       ; 4            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |MULTI8X8|ARICTL:U1|lpm_counter:CNT4B_rtl_0                         ;
;          |cntr_qu7:auto_generated| ; 4 (4)       ; 4            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |MULTI8X8|ARICTL:U1|lpm_counter:CNT4B_rtl_0|cntr_qu7:auto_generated ;
;    |REG16B:U5|                     ; 17 (17)     ; 16           ; 0           ; 0    ; 0            ; 1 (1)        ; 7 (7)             ; 9 (9)            ; 10 (10)         ; |MULTI8X8|REG16B:U5                                                 ;
;    |SREG8B:U2|                     ; 8 (8)       ; 8            ; 0           ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 7 (7)            ; 0 (0)           ; |MULTI8X8|SREG8B:U2                                                 ;
+------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------------------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/EDA_SOPC6_12/Chpt9/EXPT91_MULTI8X8/MULTI8X8.map.eqn.


+--------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                         ;
+--------------------------------------------------------------+-----------------+
; File Name                                                    ; Used in Netlist ;
+--------------------------------------------------------------+-----------------+
; ADDER4B.VHD                                                  ; yes             ;
; ADDER8B.VHD                                                  ; yes             ;
; ANDARITH.VHD                                                 ; yes             ;
; ARICTL.VHD                                                   ; yes             ;
; MULTI8X8.VHD                                                 ; yes             ;
; REG16B.VHD                                                   ; yes             ;
; SREG8B.VHD                                                   ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf  ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/lpm_constant.inc ; yes             ;
; D:/EDA_SOPC6_12/Chpt9/EXPT91_MULTI8X8/db/cntr_qu7.tdf        ; yes             ;
+--------------------------------------------------------------+-----------------+


+-------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary     ;
+-----------------------------------+-------------+
; Resource                          ; Usage       ;
+-----------------------------------+-------------+
; Logic cells                       ; 39          ;
; Total combinational functions     ; 31          ;
; Total 4-input functions           ; 0           ;
; Total 3-input functions           ; 9           ;
; Total 2-input functions           ; 16          ;
; Total 1-input functions           ; 4           ;
; Total 0-input functions           ; 2           ;
; Combinational cells for routing   ; 0           ;
; Total registers                   ; 28          ;
; Total logic cells in carry chains ; 14          ;
; I/O pins                          ; 34          ;
; Maximum fan-out node              ; NEWSTART~33 ;
; Maximum fan-out                   ; 30          ;
; Total fan-out                     ; 151         ;
; Average fan-out                   ; 2.07        ;
+-----------------------------------+-------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Tue Aug 02 07:54:57 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off MULTI8X8 -c MULTI8X8
Info: Found 2 design units, including 1 entities, in source file ADDER4B.VHD
    Info: Found design unit 1: ADDER4B-behav
    Info: Found entity 1: ADDER4B
Info: Found 2 design units, including 1 entities, in source file ADDER8B.VHD
    Info: Found design unit 1: ADDER8B-struc
    Info: Found entity 1: ADDER8B
Info: Found 2 design units, including 1 entities, in source file ANDARITH.VHD
    Info: Found design unit 1: ANDARITH-behav
    Info: Found entity 1: ANDARITH
Info: Found 2 design units, including 1 entities, in source file ARICTL.VHD
    Info: Found design unit 1: ARICTL-behav
    Info: Found entity 1: ARICTL
Info: Found 2 design units, including 1 entities, in source file MULTI8X8.VHD
    Info: Found design unit 1: MULTI8X8-struc
    Info: Found entity 1: MULTI8X8
Info: Found 2 design units, including 1 entities, in source file REG16B.VHD
    Info: Found design unit 1: REG16B-behav
    Info: Found entity 1: REG16B
Info: Found 2 design units, including 1 entities, in source file SREG8B.VHD
    Info: Found design unit 1: SREG8B-behav
    Info: Found entity 1: SREG8B
Warning: VHDL Process Statement warning at MULTI8X8.VHD(41): signal or variable newstart may not be assigned a new value in every possible path through the Process Statement. Signal or variable newstart holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Ignored 1 buffer(s)
    Info: Ignored 1 SOFT buffer(s)
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: ARICTL:U1|CNT4B[0]~0
Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus41/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file db/cntr_qu7.tdf
    Info: Found entity 1: cntr_qu7
Info: Implemented 73 device resources after synthesis - the final resource count might be different
    Info: Implemented 18 input pins
    Info: Implemented 16 output pins
    Info: Implemented 39 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Aug 02 07:55:01 2005
    Info: Elapsed time: 00:00:03