multi8x8.map.eqn

基于fpga和sopc的用VHDL语言编写的EDA移位相加硬件乘法器

--F1_R16S[15] is REG16B:U5|R16S[15]
--operation mode is normal

F1_R16S[15]_carry_eqn = F1L52;
F1_R16S[15]_lut_out = F1_R16S[15]_carry_eqn;
F1_R16S[15] = DFFEA(F1_R16S[15]_lut_out, B1L1, !A1L73, , , , );


--F1_R16S[14] is REG16B:U5|R16S[14]
--operation mode is arithmetic

F1_R16S[14]_carry_eqn = F1L32;
F1_R16S[14]_lut_out = F1_R16S[15] $ D1_DOUT[7] $ !F1_R16S[14]_carry_eqn;
F1_R16S[14] = DFFEA(F1_R16S[14]_lut_out, B1L1, !A1L73, , , , );

--F1L52 is REG16B:U5|R16S[14]~COUT
--operation mode is arithmetic

F1L52 = CARRY(F1_R16S[15] & (D1_DOUT[7] # !F1L32) # !F1_R16S[15] & D1_DOUT[7] & !F1L32);


--F1_R16S[13] is REG16B:U5|R16S[13]
--operation mode is arithmetic

F1_R16S[13]_carry_eqn = F1L12;
F1_R16S[13]_lut_out = F1_R16S[14] $ D1_DOUT[6] $ F1_R16S[13]_carry_eqn;
F1_R16S[13] = DFFEA(F1_R16S[13]_lut_out, B1L1, !A1L73, , , , );

--F1L32 is REG16B:U5|R16S[13]~COUT
--operation mode is arithmetic

F1L32 = CARRY(F1_R16S[14] & !D1_DOUT[6] & !F1L12 # !F1_R16S[14] & (!F1L12 # !D1_DOUT[6]));


--F1_R16S[12] is REG16B:U5|R16S[12]
--operation mode is arithmetic

F1_R16S[12]_carry_eqn = F1L91;
F1_R16S[12]_lut_out = F1_R16S[13] $ D1_DOUT[5] $ !F1_R16S[12]_carry_eqn;
F1_R16S[12] = DFFEA(F1_R16S[12]_lut_out, B1L1, !A1L73, , , , );

--F1L12 is REG16B:U5|R16S[12]~COUT
--operation mode is arithmetic

F1L12 = CARRY(F1_R16S[13] & (D1_DOUT[5] # !F1L91) # !F1_R16S[13] & D1_DOUT[5] & !F1L91);


--F1_R16S[11] is REG16B:U5|R16S[11]
--operation mode is arithmetic

F1_R16S[11]_carry_eqn = F1L01;
F1_R16S[11]_lut_out = F1_R16S[12] $ D1_DOUT[4] $ F1_R16S[11]_carry_eqn;
F1_R16S[11] = DFFEA(F1_R16S[11]_lut_out, B1L1, !A1L73, , , , );

--F1L91 is REG16B:U5|R16S[11]~COUT
--operation mode is arithmetic

F1L91 = CARRY(F1_R16S[12] & !D1_DOUT[4] & !F1L01 # !F1_R16S[12] & (!F1L01 # !D1_DOUT[4]));


--F1_R16S[10] is REG16B:U5|R16S[10]
--operation mode is arithmetic

F1_R16S[10]_carry_eqn = F1L51;
F1_R16S[10]_lut_out = F1_R16S[11] $ D1_DOUT[3] $ F1_R16S[10]_carry_eqn;
F1_R16S[10] = DFFEA(F1_R16S[10]_lut_out, B1L1, !A1L73, , , , );

--F1L71 is REG16B:U5|R16S[10]~COUT
--operation mode is arithmetic

F1L71 = CARRY(F1_R16S[11] & !D1_DOUT[3] & !F1L51 # !F1_R16S[11] & (!F1L51 # !D1_DOUT[3]));


--F1_R16S[9] is REG16B:U5|R16S[9]
--operation mode is arithmetic

F1_R16S[9]_carry_eqn = F1L31;
F1_R16S[9]_lut_out = F1_R16S[10] $ D1_DOUT[2] $ !F1_R16S[9]_carry_eqn;
F1_R16S[9] = DFFEA(F1_R16S[9]_lut_out, B1L1, !A1L73, , , , );

--F1L51 is REG16B:U5|R16S[9]~COUT
--operation mode is arithmetic

F1L51 = CARRY(F1_R16S[10] & (D1_DOUT[2] # !F1L31) # !F1_R16S[10] & D1_DOUT[2] & !F1L31);


--F1_R16S[8] is REG16B:U5|R16S[8]
--operation mode is arithmetic

F1_R16S[8]_carry_eqn = F1L11;
F1_R16S[8]_lut_out = F1_R16S[9] $ D1_DOUT[1] $ F1_R16S[8]_carry_eqn;
F1_R16S[8] = DFFEA(F1_R16S[8]_lut_out, B1L1, !A1L73, , , , );

--F1L31 is REG16B:U5|R16S[8]~COUT
--operation mode is arithmetic

F1L31 = CARRY(F1_R16S[9] & !D1_DOUT[1] & !F1L11 # !F1_R16S[9] & (!F1L11 # !D1_DOUT[1]));


--F1_R16S[7] is REG16B:U5|R16S[7]
--operation mode is arithmetic

F1_R16S[7]_lut_out = F1_R16S[8] $ D1_DOUT[0];
F1_R16S[7] = DFFEA(F1_R16S[7]_lut_out, B1L1, !A1L73, , , , );

--F1L11 is REG16B:U5|R16S[7]~COUT
--operation mode is arithmetic

F1L11 = CARRY(F1_R16S[8] & D1_DOUT[0]);


--F1_R16S[6] is REG16B:U5|R16S[6]
--operation mode is normal

F1_R16S[6]_lut_out = F1_R16S[7];
F1_R16S[6] = DFFEA(F1_R16S[6]_lut_out, B1L1, !A1L73, , , , );


--F1_R16S[5] is REG16B:U5|R16S[5]
--operation mode is normal

F1_R16S[5]_lut_out = F1_R16S[6];
F1_R16S[5] = DFFEA(F1_R16S[5]_lut_out, B1L1, !A1L73, , , , );


--F1_R16S[4] is REG16B:U5|R16S[4]
--operation mode is normal

F1_R16S[4]_lut_out = F1_R16S[5];
F1_R16S[4] = DFFEA(F1_R16S[4]_lut_out, B1L1, !A1L73, , , , );


--F1_R16S[3] is REG16B:U5|R16S[3]
--operation mode is normal

F1_R16S[3]_lut_out = F1_R16S[4];
F1_R16S[3] = DFFEA(F1_R16S[3]_lut_out, B1L1, !A1L73, , , , );


--F1_R16S[2] is REG16B:U5|R16S[2]
--operation mode is normal

F1_R16S[2]_lut_out = F1_R16S[3];
F1_R16S[2] = DFFEA(F1_R16S[2]_lut_out, B1L1, !A1L73, , , , );


--F1_R16S[1] is REG16B:U5|R16S[1]
--operation mode is normal

F1_R16S[1]_lut_out = F1_R16S[2];
F1_R16S[1] = DFFEA(F1_R16S[1]_lut_out, B1L1, !A1L73, , , , );


--F1_R16S[0] is REG16B:U5|R16S[0]
--operation mode is normal

F1_R16S[0]_lut_out = F1_R16S[1];
F1_R16S[0] = DFFEA(F1_R16S[0]_lut_out, B1L1, !A1L73, , , , );


--H1_safe_q[3] is ARICTL:U1|lpm_counter:CNT4B_rtl_0|cntr_qu7:auto_generated|safe_q[3]
--operation mode is normal

H1_safe_q[3]_carry_eqn = H1L6;
H1_safe_q[3]_lut_out = H1_safe_q[3] $ H1_safe_q[3]_carry_eqn;
H1_safe_q[3] = DFFEA(H1_safe_q[3]_lut_out, CLKK, !A1L73, , !H1_safe_q[3], , );


--B1L1 is ARICTL:U1|CLKOUT~24
--operation mode is normal

B1L1 = CLKK & (A1L73 # !H1_safe_q[3]);


--C1_REG8[0] is SREG8B:U2|REG8[0]
--operation mode is normal

C1_REG8[0]_lut_out = B[0] & (C1_REG8[1] # A1L73) # !B[0] & C1_REG8[1] & !A1L73;
C1_REG8[0] = DFFEA(C1_REG8[0]_lut_out, B1L1, VCC, , , , );


--D1_DOUT[7] is ANDARITH:U3|DOUT[7]
--operation mode is normal

D1_DOUT[7] = C1_REG8[0] & A[7];


--D1_DOUT[6] is ANDARITH:U3|DOUT[6]
--operation mode is normal

D1_DOUT[6] = C1_REG8[0] & A[6];


--D1_DOUT[5] is ANDARITH:U3|DOUT[5]
--operation mode is normal

D1_DOUT[5] = C1_REG8[0] & A[5];


--D1_DOUT[4] is ANDARITH:U3|DOUT[4]
--operation mode is normal

D1_DOUT[4] = C1_REG8[0] & A[4];


--F1L01 is REG16B:U5|R16S[7]~0
--operation mode is arithmetic

F1L01 = CARRY(!F1L71);


--D1_DOUT[3] is ANDARITH:U3|DOUT[3]
--operation mode is normal

D1_DOUT[3] = C1_REG8[0] & A[3];


--D1_DOUT[2] is ANDARITH:U3|DOUT[2]
--operation mode is normal

D1_DOUT[2] = C1_REG8[0] & A[2];


--D1_DOUT[1] is ANDARITH:U3|DOUT[1]
--operation mode is normal

D1_DOUT[1] = C1_REG8[0] & A[1];


--D1_DOUT[0] is ANDARITH:U3|DOUT[0]
--operation mode is normal

D1_DOUT[0] = C1_REG8[0] & A[0];


--A1L73 is NEWSTART~33
--operation mode is normal

A1L73 = LCELL(START # A1L73 & CLKK);


--H1_safe_q[2] is ARICTL:U1|lpm_counter:CNT4B_rtl_0|cntr_qu7:auto_generated|safe_q[2]
--operation mode is arithmetic

H1_safe_q[2]_carry_eqn = H1L4;
H1_safe_q[2]_lut_out = H1_safe_q[2] $ !H1_safe_q[2]_carry_eqn;
H1_safe_q[2] = DFFEA(H1_safe_q[2]_lut_out, CLKK, !A1L73, , !H1_safe_q[3], , );

--H1L6 is ARICTL:U1|lpm_counter:CNT4B_rtl_0|cntr_qu7:auto_generated|counter_cella2~COUT
--operation mode is arithmetic

H1L6 = CARRY(H1_safe_q[2] & !H1L4);


--C1_REG8[1] is SREG8B:U2|REG8[1]
--operation mode is normal

C1_REG8[1]_lut_out = B[1] & (C1_REG8[2] # A1L73) # !B[1] & C1_REG8[2] & !A1L73;
C1_REG8[1] = DFFEA(C1_REG8[1]_lut_out, B1L1, VCC, , , , );


--H1_safe_q[1] is ARICTL:U1|lpm_counter:CNT4B_rtl_0|cntr_qu7:auto_generated|safe_q[1]
--operation mode is arithmetic

H1_safe_q[1]_carry_eqn = H1L2;
H1_safe_q[1]_lut_out = H1_safe_q[1] $ H1_safe_q[1]_carry_eqn;
H1_safe_q[1] = DFFEA(H1_safe_q[1]_lut_out, CLKK, !A1L73, , !H1_safe_q[3], , );

--H1L4 is ARICTL:U1|lpm_counter:CNT4B_rtl_0|cntr_qu7:auto_generated|counter_cella1~COUT
--operation mode is arithmetic

H1L4 = CARRY(!H1L2 # !H1_safe_q[1]);


--C1_REG8[2] is SREG8B:U2|REG8[2]
--operation mode is normal

C1_REG8[2]_lut_out = B[2] & (C1_REG8[3] # A1L73) # !B[2] & C1_REG8[3] & !A1L73;
C1_REG8[2] = DFFEA(C1_REG8[2]_lut_out, B1L1, VCC, , , , );


--H1_safe_q[0] is ARICTL:U1|lpm_counter:CNT4B_rtl_0|cntr_qu7:auto_generated|safe_q[0]
--operation mode is arithmetic

H1_safe_q[0]_lut_out = !H1_safe_q[0];
H1_safe_q[0] = DFFEA(H1_safe_q[0]_lut_out, CLKK, !A1L73, , !H1_safe_q[3], , );

--H1L2 is ARICTL:U1|lpm_counter:CNT4B_rtl_0|cntr_qu7:auto_generated|counter_cella0~COUT
--operation mode is arithmetic

H1L2 = CARRY(H1_safe_q[0]);


--C1_REG8[3] is SREG8B:U2|REG8[3]
--operation mode is normal

C1_REG8[3]_lut_out = B[3] & (C1_REG8[4] # A1L73) # !B[3] & C1_REG8[4] & !A1L73;
C1_REG8[3] = DFFEA(C1_REG8[3]_lut_out, B1L1, VCC, , , , );


--C1_REG8[4] is SREG8B:U2|REG8[4]
--operation mode is normal

C1_REG8[4]_lut_out = B[4] & (C1_REG8[5] # A1L73) # !B[4] & C1_REG8[5] & !A1L73;
C1_REG8[4] = DFFEA(C1_REG8[4]_lut_out, B1L1, VCC, , , , );


--C1_REG8[5] is SREG8B:U2|REG8[5]
--operation mode is normal

C1_REG8[5]_lut_out = B[5] & (C1_REG8[6] # A1L73) # !B[5] & C1_REG8[6] & !A1L73;
C1_REG8[5] = DFFEA(C1_REG8[5]_lut_out, B1L1, VCC, , , , );


--C1_REG8[6] is SREG8B:U2|REG8[6]
--operation mode is normal

C1_REG8[6]_lut_out = B[6] & (C1_REG8[7] # A1L73) # !B[6] & C1_REG8[7] & !A1L73;
C1_REG8[6] = DFFEA(C1_REG8[6]_lut_out, B1L1, VCC, , , , );


--C1_REG8[7] is SREG8B:U2|REG8[7]
--operation mode is normal

C1_REG8[7]_lut_out = B[7];
C1_REG8[7] = DFFEA(C1_REG8[7]_lut_out, B1L1, VCC, , A1L73, , );


--CLKK is CLKK
--operation mode is input

CLKK = INPUT();


--A[7] is A[7]
--operation mode is input

A[7] = INPUT();


--A[6] is A[6]
--operation mode is input

A[6] = INPUT();


--A[5] is A[5]
--operation mode is input

A[5] = INPUT();


--A[4] is A[4]
--operation mode is input

A[4] = INPUT();


--A[3] is A[3]
--operation mode is input

A[3] = INPUT();


--A[2] is A[2]
--operation mode is input

A[2] = INPUT();


--A[1] is A[1]
--operation mode is input

A[1] = INPUT();


--A[0] is A[0]
--operation mode is input

A[0] = INPUT();


--START is START
--operation mode is input

START = INPUT();


--B[0] is B[0]
--operation mode is input

B[0] = INPUT();


--B[1] is B[1]
--operation mode is input

B[1] = INPUT();


--B[2] is B[2]
--operation mode is input

B[2] = INPUT();


--B[3] is B[3]
--operation mode is input

B[3] = INPUT();


--B[4] is B[4]
--operation mode is input

B[4] = INPUT();


--B[5] is B[5]
--operation mode is input

B[5] = INPUT();


--B[6] is B[6]
--operation mode is input

B[6] = INPUT();


--B[7] is B[7]
--operation mode is input

B[7] = INPUT();


--DOUT[15] is DOUT[15]
--operation mode is output

DOUT[15] = OUTPUT(F1_R16S[15]);


--DOUT[14] is DOUT[14]
--operation mode is output

DOUT[14] = OUTPUT(F1_R16S[14]);


--DOUT[13] is DOUT[13]
--operation mode is output

DOUT[13] = OUTPUT(F1_R16S[13]);


--DOUT[12] is DOUT[12]
--operation mode is output

DOUT[12] = OUTPUT(F1_R16S[12]);


--DOUT[11] is DOUT[11]
--operation mode is output

DOUT[11] = OUTPUT(F1_R16S[11]);


--DOUT[10] is DOUT[10]
--operation mode is output

DOUT[10] = OUTPUT(F1_R16S[10]);


--DOUT[9] is DOUT[9]
--operation mode is output

DOUT[9] = OUTPUT(F1_R16S[9]);


--DOUT[8] is DOUT[8]
--operation mode is output

DOUT[8] = OUTPUT(F1_R16S[8]);


--DOUT[7] is DOUT[7]
--operation mode is output

DOUT[7] = OUTPUT(F1_R16S[7]);


--DOUT[6] is DOUT[6]
--operation mode is output

DOUT[6] = OUTPUT(F1_R16S[6]);


--DOUT[5] is DOUT[5]
--operation mode is output

DOUT[5] = OUTPUT(F1_R16S[5]);


--DOUT[4] is DOUT[4]
--operation mode is output

DOUT[4] = OUTPUT(F1_R16S[4]);


--DOUT[3] is DOUT[3]
--operation mode is output

DOUT[3] = OUTPUT(F1_R16S[3]);


--DOUT[2] is DOUT[2]
--operation mode is output

DOUT[2] = OUTPUT(F1_R16S[2]);


--DOUT[1] is DOUT[1]
--operation mode is output

DOUT[1] = OUTPUT(F1_R16S[1]);


--DOUT[0] is DOUT[0]
--operation mode is output

DOUT[0] = OUTPUT(F1_R16S[0]);