dac2adc.map.summary

基于fpga和sopc的用VHDL语言编写的EDA比较器和D/A器件实现

Flow Status : Successful - Tue Aug 02 07:46:01 2005
Quartus II Version : 4.1 Build 181 06/29/2004 SJ Full Version
Revision Name : DAC2ADC
Top-level Entity Name : DAC2ADC
Family : Cyclone
Device : EP1C6Q240C8
Timing Models : Production
Total logic elements : 16
Total pins : 19
Total memory bits : 0
Total PLLs : 0