cnt10b.bsf

基于fpga和sopc的用VHDL语言编写的EDA数据采集电路和简易存储示波器

/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
*/
(header "symbol" (version "1.1"))
(symbol
	(rect 16 16 160 144)
	(text "CNT10B" (rect 5 0 46 12)(font "Arial" ))
	(text "inst" (rect 8 112 25 124)(font "Arial" ))
	(port
		(pt 0 32)
		(input)
		(text "LOCK0" (rect 0 0 35 12)(font "Arial" ))
		(text "LOCK0" (rect 21 27 56 39)(font "Arial" ))
		(line (pt 0 32)(pt 16 32)(line_width 1))
	)
	(port
		(pt 0 48)
		(input)
		(text "CLR" (rect 0 0 22 12)(font "Arial" ))
		(text "CLR" (rect 21 43 43 55)(font "Arial" ))
		(line (pt 0 48)(pt 16 48)(line_width 1))
	)
	(port
		(pt 0 64)
		(input)
		(text "CLK" (rect 0 0 21 12)(font "Arial" ))
		(text "CLK" (rect 21 59 42 71)(font "Arial" ))
		(line (pt 0 64)(pt 16 64)(line_width 1))
	)
	(port
		(pt 0 80)
		(input)
		(text "WE" (rect 0 0 17 12)(font "Arial" ))
		(text "WE" (rect 21 75 38 87)(font "Arial" ))
		(line (pt 0 80)(pt 16 80)(line_width 1))
	)
	(port
		(pt 144 32)
		(output)
		(text "DOUT[8..0]" (rect 0 0 56 12)(font "Arial" ))
		(text "DOUT[8..0]" (rect 67 27 123 39)(font "Arial" ))
		(line (pt 144 32)(pt 128 32)(line_width 3))
	)
	(port
		(pt 144 48)
		(output)
		(text "CLKOUT" (rect 0 0 43 12)(font "Arial" ))
		(text "CLKOUT" (rect 80 43 123 55)(font "Arial" ))
		(line (pt 144 48)(pt 128 48)(line_width 1))
	)
	(drawing
		(rectangle (rect 16 16 128 112)(line_width 1))
	)
)