resv.qsf

基于fpga和sopc的用VHDL语言编写的EDA数据采集电路和简易存储示波器

# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		RESV_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:06:21  FEBRUARY 02, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION 4.1
set_global_assignment -name VHDL_FILE ADCINT.vhd
set_global_assignment -name VHDL_FILE CNT10B.vhd
set_global_assignment -name VHDL_FILE RAM8B.vhd
set_global_assignment -name BDF_FILE RESV.bdf

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_137 -to ADDA
set_location_assignment PIN_138 -to ALE
set_location_assignment PIN_28 -to CLK
set_location_assignment PIN_233 -to CLR
set_location_assignment PIN_1 -to EOC
set_location_assignment PIN_140 -to OE
set_location_assignment PIN_139 -to START
set_location_assignment PIN_234 -to WREN
set_location_assignment PIN_13 -to D\[0\]
set_location_assignment PIN_14 -to D\[1\]
set_location_assignment PIN_15 -to D\[2\]
set_location_assignment PIN_16 -to D\[3\]
set_location_assignment PIN_17 -to D\[4\]
set_location_assignment PIN_18 -to D\[5\]
set_location_assignment PIN_19 -to D\[6\]
set_location_assignment PIN_20 -to D\[7\]
set_location_assignment PIN_21 -to Q\[0\]
set_location_assignment PIN_41 -to Q\[1\]
set_location_assignment PIN_128 -to Q\[2\]
set_location_assignment PIN_132 -to Q\[3\]
set_location_assignment PIN_133 -to Q\[4\]
set_location_assignment PIN_134 -to Q\[5\]
set_location_assignment PIN_135 -to Q\[6\]
set_location_assignment PIN_136 -to Q\[7\]

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PACKAGE PQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name TOP_LEVEL_ENTITY RESV

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1C6Q240C8

# LogicLock Region Assignments
# ============================
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT off