resv.fit.summary

基于fpga和sopc的用VHDL语言编写的EDA数据采集电路和简易存储示波器

Flow Status : Successful - Tue Aug 02 07:33:11 2005
Quartus II Version : 4.1 Build 181 06/29/2004 SJ Full Version
Revision Name : RESV
Top-level Entity Name : RESV
Family : Cyclone
Device : EP1C6Q240C8
Timing Models : Production
Total logic elements : 185 / 5,980 ( 3 % )
Total pins : 24 / 185 ( 12 % )
Total memory bits : 4,096 / 92,160 ( 4 % )
Total PLLs : 0 / 2 ( 0 % )