cnt10b.vhd

基于fpga和sopc的用VHDL语言编写的EDA数据采集电路和简易存储示波器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT10B IS
      PORT (LOCK0,CLR : IN STD_LOGIC; 
                  CLK : IN STD_LOGIC;
                   WE : IN STD_LOGIC;
                 DOUT : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
               CLKOUT : OUT STD_LOGIC );
     END CNT10B;
ARCHITECTURE behav OF CNT10B IS
      SIGNAL CQI  :  STD_LOGIC_VECTOR(8 DOWNTO 0);
      SIGNAL CLK0 :  STD_LOGIC;
BEGIN
CLK0 <= LOCK0 WHEN WE='1' ELSE
        CLK;
  PROCESS(CLK0,CLR,CQI)
   BEGIN
    IF CLR = '1' THEN  CQI <= "000000000";
    ELSIF CLK0'EVENT AND CLK0 = '1' THEN  CQI <= CQI + 1; END IF;
  END PROCESS;
        DOUT <= CQI; CLKOUT <= CLK0;
END behav;