resv.fit.eqn

基于fpga和sopc的用VHDL语言编写的EDA数据采集电路和简易存储示波器

--B1L2Q is ADCINT:inst|current_state~11 at LC_X8_Y10_N4
--operation mode is normal

B1L2Q_lut_out = !B1L1Q;
B1L2Q = DFFEA(B1L2Q_lut_out, GLOBAL(CLK), VCC, , , , );


--B1L4Q is ADCINT:inst|current_state~13 at LC_X8_Y10_N9
--operation mode is normal

B1L4Q_lut_out = B1L3Q & EOC;
B1L4Q = DFFEA(B1L4Q_lut_out, GLOBAL(CLK), VCC, , , , );


--B1_OE is ADCINT:inst|OE at LC_X8_Y10_N5
--operation mode is normal

B1L5Q_qfbk = B1L5Q;
B1_OE = B1L4Q # B1L5Q_qfbk;

--B1L5Q is ADCINT:inst|current_state~14 at LC_X8_Y10_N5
--operation mode is normal

B1L5Q_sload_eqn = B1L4Q;
B1L5Q = DFFEA(B1L5Q_sload_eqn, GLOBAL(CLK), VCC, , , , );


--H1_q_a[7] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|altsyncram_3fb2:altsyncram1|q_a[7] at M4K_X17_Y7
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 512, Port B Width: 8
--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
H1_q_a[7]_PORT_A_data_in = BUS(B1_REGL[7], B1_REGL[6], B1_REGL[5], B1_REGL[4], B1_REGL[3], B1_REGL[2], B1_REGL[1], B1_REGL[0]);
H1_q_a[7]_PORT_A_data_in_reg = DFFE(H1_q_a[7]_PORT_A_data_in, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_PORT_B_data_in = BUS(J1_ram_rom_data_reg[7], J1_ram_rom_data_reg[6], J1_ram_rom_data_reg[5], J1_ram_rom_data_reg[4], J1_ram_rom_data_reg[3], J1_ram_rom_data_reg[2], J1_ram_rom_data_reg[1], J1_ram_rom_data_reg[0]);
H1_q_a[7]_PORT_B_data_in_reg = DFFE(H1_q_a[7]_PORT_B_data_in, H1_q_a[7]_clock_1, , , );
H1_q_a[7]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8]);
H1_q_a[7]_PORT_A_address_reg = DFFE(H1_q_a[7]_PORT_A_address, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_PORT_B_address = BUS(M1_safe_q[0], M1_safe_q[1], M1_safe_q[2], M1_safe_q[3], M1_safe_q[4], M1_safe_q[5], M1_safe_q[6], M1_safe_q[7], M1_safe_q[8]);
H1_q_a[7]_PORT_B_address_reg = DFFE(H1_q_a[7]_PORT_B_address, H1_q_a[7]_clock_1, , , );
H1_q_a[7]_PORT_A_write_enable = WREN;
H1_q_a[7]_PORT_A_write_enable_reg = DFFE(H1_q_a[7]_PORT_A_write_enable, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_PORT_B_write_enable = J1L23;
H1_q_a[7]_PORT_B_write_enable_reg = DFFE(H1_q_a[7]_PORT_B_write_enable, H1_q_a[7]_clock_1, , , );
H1_q_a[7]_clock_0 = GLOBAL(D1L1);
H1_q_a[7]_clock_1 = GLOBAL(A1L7);
H1_q_a[7]_PORT_A_data_out = MEMORY(H1_q_a[7]_PORT_A_data_in_reg, H1_q_a[7]_PORT_B_data_in_reg, H1_q_a[7]_PORT_A_address_reg, H1_q_a[7]_PORT_B_address_reg, H1_q_a[7]_PORT_A_write_enable_reg, H1_q_a[7]_PORT_B_write_enable_reg, , , H1_q_a[7]_clock_0, H1_q_a[7]_clock_1, , , , );
H1_q_a[7] = H1_q_a[7]_PORT_A_data_out[0];

--H1_q_b[7] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|altsyncram_3fb2:altsyncram1|q_b[7] at M4K_X17_Y7
H1_q_b[7]_PORT_A_data_in = BUS(B1_REGL[7], B1_REGL[6], B1_REGL[5], B1_REGL[4], B1_REGL[3], B1_REGL[2], B1_REGL[1], B1_REGL[0]);
H1_q_b[7]_PORT_A_data_in_reg = DFFE(H1_q_b[7]_PORT_A_data_in, H1_q_b[7]_clock_0, , , );
H1_q_b[7]_PORT_B_data_in = BUS(J1_ram_rom_data_reg[7], J1_ram_rom_data_reg[6], J1_ram_rom_data_reg[5], J1_ram_rom_data_reg[4], J1_ram_rom_data_reg[3], J1_ram_rom_data_reg[2], J1_ram_rom_data_reg[1], J1_ram_rom_data_reg[0]);
H1_q_b[7]_PORT_B_data_in_reg = DFFE(H1_q_b[7]_PORT_B_data_in, H1_q_b[7]_clock_1, , , );
H1_q_b[7]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8]);
H1_q_b[7]_PORT_A_address_reg = DFFE(H1_q_b[7]_PORT_A_address, H1_q_b[7]_clock_0, , , );
H1_q_b[7]_PORT_B_address = BUS(M1_safe_q[0], M1_safe_q[1], M1_safe_q[2], M1_safe_q[3], M1_safe_q[4], M1_safe_q[5], M1_safe_q[6], M1_safe_q[7], M1_safe_q[8]);
H1_q_b[7]_PORT_B_address_reg = DFFE(H1_q_b[7]_PORT_B_address, H1_q_b[7]_clock_1, , , );
H1_q_b[7]_PORT_A_write_enable = WREN;
H1_q_b[7]_PORT_A_write_enable_reg = DFFE(H1_q_b[7]_PORT_A_write_enable, H1_q_b[7]_clock_0, , , );
H1_q_b[7]_PORT_B_write_enable = J1L23;
H1_q_b[7]_PORT_B_write_enable_reg = DFFE(H1_q_b[7]_PORT_B_write_enable, H1_q_b[7]_clock_1, , , );
H1_q_b[7]_clock_0 = GLOBAL(D1L1);
H1_q_b[7]_clock_1 = GLOBAL(A1L7);
H1_q_b[7]_PORT_B_data_out = MEMORY(H1_q_b[7]_PORT_A_data_in_reg, H1_q_b[7]_PORT_B_data_in_reg, H1_q_b[7]_PORT_A_address_reg, H1_q_b[7]_PORT_B_address_reg, H1_q_b[7]_PORT_A_write_enable_reg, H1_q_b[7]_PORT_B_write_enable_reg, , , H1_q_b[7]_clock_0, H1_q_b[7]_clock_1, , , , );
H1_q_b[7] = H1_q_b[7]_PORT_B_data_out[0];

--H1_q_a[0] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|altsyncram_3fb2:altsyncram1|q_a[0] at M4K_X17_Y7
H1_q_a[7]_PORT_A_data_in = BUS(B1_REGL[7], B1_REGL[6], B1_REGL[5], B1_REGL[4], B1_REGL[3], B1_REGL[2], B1_REGL[1], B1_REGL[0]);
H1_q_a[7]_PORT_A_data_in_reg = DFFE(H1_q_a[7]_PORT_A_data_in, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_PORT_B_data_in = BUS(J1_ram_rom_data_reg[7], J1_ram_rom_data_reg[6], J1_ram_rom_data_reg[5], J1_ram_rom_data_reg[4], J1_ram_rom_data_reg[3], J1_ram_rom_data_reg[2], J1_ram_rom_data_reg[1], J1_ram_rom_data_reg[0]);
H1_q_a[7]_PORT_B_data_in_reg = DFFE(H1_q_a[7]_PORT_B_data_in, H1_q_a[7]_clock_1, , , );
H1_q_a[7]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8]);
H1_q_a[7]_PORT_A_address_reg = DFFE(H1_q_a[7]_PORT_A_address, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_PORT_B_address = BUS(M1_safe_q[0], M1_safe_q[1], M1_safe_q[2], M1_safe_q[3], M1_safe_q[4], M1_safe_q[5], M1_safe_q[6], M1_safe_q[7], M1_safe_q[8]);
H1_q_a[7]_PORT_B_address_reg = DFFE(H1_q_a[7]_PORT_B_address, H1_q_a[7]_clock_1, , , );
H1_q_a[7]_PORT_A_write_enable = WREN;
H1_q_a[7]_PORT_A_write_enable_reg = DFFE(H1_q_a[7]_PORT_A_write_enable, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_PORT_B_write_enable = J1L23;
H1_q_a[7]_PORT_B_write_enable_reg = DFFE(H1_q_a[7]_PORT_B_write_enable, H1_q_a[7]_clock_1, , , );
H1_q_a[7]_clock_0 = GLOBAL(D1L1);
H1_q_a[7]_clock_1 = GLOBAL(A1L7);
H1_q_a[7]_PORT_A_data_out = MEMORY(H1_q_a[7]_PORT_A_data_in_reg, H1_q_a[7]_PORT_B_data_in_reg, H1_q_a[7]_PORT_A_address_reg, H1_q_a[7]_PORT_B_address_reg, H1_q_a[7]_PORT_A_write_enable_reg, H1_q_a[7]_PORT_B_write_enable_reg, , , H1_q_a[7]_clock_0, H1_q_a[7]_clock_1, , , , );
H1_q_a[0] = H1_q_a[7]_PORT_A_data_out[7];

--H1_q_a[1] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|altsyncram_3fb2:altsyncram1|q_a[1] at M4K_X17_Y7
H1_q_a[7]_PORT_A_data_in = BUS(B1_REGL[7], B1_REGL[6], B1_REGL[5], B1_REGL[4], B1_REGL[3], B1_REGL[2], B1_REGL[1], B1_REGL[0]);
H1_q_a[7]_PORT_A_data_in_reg = DFFE(H1_q_a[7]_PORT_A_data_in, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_PORT_B_data_in = BUS(J1_ram_rom_data_reg[7], J1_ram_rom_data_reg[6], J1_ram_rom_data_reg[5], J1_ram_rom_data_reg[4], J1_ram_rom_data_reg[3], J1_ram_rom_data_reg[2], J1_ram_rom_data_reg[1], J1_ram_rom_data_reg[0]);
H1_q_a[7]_PORT_B_data_in_reg = DFFE(H1_q_a[7]_PORT_B_data_in, H1_q_a[7]_clock_1, , , );
H1_q_a[7]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8]);
H1_q_a[7]_PORT_A_address_reg = DFFE(H1_q_a[7]_PORT_A_address, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_PORT_B_address = BUS(M1_safe_q[0], M1_safe_q[1], M1_safe_q[2], M1_safe_q[3], M1_safe_q[4], M1_safe_q[5], M1_safe_q[6], M1_safe_q[7], M1_safe_q[8]);
H1_q_a[7]_PORT_B_address_reg = DFFE(H1_q_a[7]_PORT_B_address, H1_q_a[7]_clock_1, , , );
H1_q_a[7]_PORT_A_write_enable = WREN;
H1_q_a[7]_PORT_A_write_enable_reg = DFFE(H1_q_a[7]_PORT_A_write_enable, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_PORT_B_write_enable = J1L23;
H1_q_a[7]_PORT_B_write_enable_reg = DFFE(H1_q_a[7]_PORT_B_write_enable, H1_q_a[7]_clock_1, , , );
H1_q_a[7]_clock_0 = GLOBAL(D1L1);
H1_q_a[7]_clock_1 = GLOBAL(A1L7);
H1_q_a[7]_PORT_A_data_out = MEMORY(H1_q_a[7]_PORT_A_data_in_reg, H1_q_a[7]_PORT_B_data_in_reg, H1_q_a[7]_PORT_A_address_reg, H1_q_a[7]_PORT_B_address_reg, H1_q_a[7]_PORT_A_write_enable_reg, H1_q_a[7]_PORT_B_write_enable_reg, , , H1_q_a[7]_clock_0, H1_q_a[7]_clock_1, , , , );
H1_q_a[1] = H1_q_a[7]_PORT_A_data_out[6];

--H1_q_a[2] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|altsyncram_3fb2:altsyncram1|q_a[2] at M4K_X17_Y7
H1_q_a[7]_PORT_A_data_in = BUS(B1_REGL[7], B1_REGL[6], B1_REGL[5], B1_REGL[4], B1_REGL[3], B1_REGL[2], B1_REGL[1], B1_REGL[0]);
H1_q_a[7]_PORT_A_data_in_reg = DFFE(H1_q_a[7]_PORT_A_data_in, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_PORT_B_data_in = BUS(J1_ram_rom_data_reg[7], J1_ram_rom_data_reg[6], J1_ram_rom_data_reg[5], J1_ram_rom_data_reg[4], J1_ram_rom_data_reg[3], J1_ram_rom_data_reg[2], J1_ram_rom_data_reg[1], J1_ram_rom_data_reg[0]);
H1_q_a[7]_PORT_B_data_in_reg = DFFE(H1_q_a[7]_PORT_B_data_in, H1_q_a[7]_clock_1, , , );
H1_q_a[7]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8]);
H1_q_a[7]_PORT_A_address_reg = DFFE(H1_q_a[7]_PORT_A_address, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_PORT_B_address = BUS(M1_safe_q[0], M1_safe_q[1], M1_safe_q[2], M1_safe_q[3], M1_safe_q[4], M1_safe_q[5], M1_safe_q[6], M1_safe_q[7], M1_safe_q[8]);
H1_q_a[7]_PORT_B_address_reg = DFFE(H1_q_a[7]_PORT_B_address, H1_q_a[7]_clock_1, , , );
H1_q_a[7]_PORT_A_write_enable = WREN;
H1_q_a[7]_PORT_A_write_enable_reg = DFFE(H1_q_a[7]_PORT_A_write_enable, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_PORT_B_write_enable = J1L23;
H1_q_a[7]_PORT_B_write_enable_reg = DFFE(H1_q_a[7]_PORT_B_write_enable, H1_q_a[7]_clock_1, , , );
H1_q_a[7]_clock_0 = GLOBAL(D1L1);
H1_q_a[7]_clock_1 = GLOBAL(A1L7);
H1_q_a[7]_PORT_A_data_out = MEMORY(H1_q_a[7]_PORT_A_data_in_reg, H1_q_a[7]_PORT_B_data_in_reg, H1_q_a[7]_PORT_A_address_reg, H1_q_a[7]_PORT_B_address_reg, H1_q_a[7]_PORT_A_write_enable_reg, H1_q_a[7]_PORT_B_write_enable_reg, , , H1_q_a[7]_clock_0, H1_q_a[7]_clock_1, , , , );
H1_q_a[2] = H1_q_a[7]_PORT_A_data_out[5];

--H1_q_a[3] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|altsyncram_3fb2:altsyncram1|q_a[3] at M4K_X17_Y7
H1_q_a[7]_PORT_A_data_in = BUS(B1_REGL[7], B1_REGL[6], B1_REGL[5], B1_REGL[4], B1_REGL[3], B1_REGL[2], B1_REGL[1], B1_REGL[0]);
H1_q_a[7]_PORT_A_data_in_reg = DFFE(H1_q_a[7]_PORT_A_data_in, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_PORT_B_data_in = BUS(J1_ram_rom_data_reg[7], J1_ram_rom_data_reg[6], J1_ram_rom_data_reg[5], J1_ram_rom_data_reg[4], J1_ram_rom_data_reg[3], J1_ram_rom_data_reg[2], J1_ram_rom_data_reg[1], J1_ram_rom_data_reg[0]);
H1_q_a[7]_PORT_B_data_in_reg = DFFE(H1_q_a[7]_PORT_B_data_in, H1_q_a[7]_clock_1, , , );
H1_q_a[7]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8]);
H1_q_a[7]_PORT_A_address_reg = DFFE(H1_q_a[7]_PORT_A_address, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_PORT_B_address = BUS(M1_safe_q[0], M1_safe_q[1], M1_safe_q[2], M1_safe_q[3], M1_safe_q[4], M1_safe_q[5], M1_safe_q[6], M1_safe_q[7], M1_safe_q[8]);
H1_q_a[7]_PORT_B_address_reg = DFFE(H1_q_a[7]_PORT_B_address, H1_q_a[7]_clock_1, , , );
H1_q_a[7]_PORT_A_write_enable = WREN;
H1_q_a[7]_PORT_A_write_enable_reg = DFFE(H1_q_a[7]_PORT_A_write_enable, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_PORT_B_write_enable = J1L23;
H1_q_a[7]_PORT_B_write_enable_reg = DFFE(H1_q_a[7]_PORT_B_write_enable, H1_q_a[7]_clock_1, , , );
H1_q_a[7]_clock_0 = GLOBAL(D1L1);
H1_q_a[7]_clock_1 = GLOBAL(A1L7);
H1_q_a[7]_PORT_A_data_out = MEMORY(H1_q_a[7]_PORT_A_data_in_reg, H1_q_a[7]_PORT_B_data_in_reg, H1_q_a[7]_PORT_A_address_reg, H1_q_a[7]_PORT_B_address_reg, H1_q_a[7]_PORT_A_write_enable_reg, H1_q_a[7]_PORT_B_write_enable_reg, , , H1_q_a[7]_clock_0, H1_q_a[7]_clock_1, , , , );
H1_q_a[3] = H1_q_a[7]_PORT_A_data_out[4];

--H1_q_a[4] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|altsyncram_3fb2:altsyncram1|q_a[4] at M4K_X17_Y7
H1_q_a[7]_PORT_A_data_in = BUS(B1_REGL[7], B1_REGL[6], B1_REGL[5], B1_REGL[4], B1_REGL[3], B1_REGL[2], B1_REGL[1], B1_REGL[0]);
H1_q_a[7]_PORT_A_data_in_reg = DFFE(H1_q_a[7]_PORT_A_data_in, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_PORT_B_data_in = BUS(J1_ram_rom_data_reg[7], J1_ram_rom_data_reg[6], J1_ram_rom_data_reg[5], J1_ram_rom_data_reg[4], J1_ram_rom_data_reg[3], J1_ram_rom_data_reg[2], J1_ram_rom_data_reg[1], J1_ram_rom_data_reg[0]);
H1_q_a[7]_PORT_B_data_in_reg = DFFE(H1_q_a[7]_PORT_B_data_in, H1_q_a[7]_clock_1, , , );
H1_q_a[7]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8]);
H1_q_a[7]_PORT_A_address_reg = DFFE(H1_q_a[7]_PORT_A_address, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_PORT_B_address = BUS(M1_safe_q[0], M1_safe_q[1], M1_safe_q[2], M1_safe_q[3], M1_safe_q[4], M1_safe_q[5], M1_safe_q[6], M1_safe_q[7], M1_safe_q[8]);
H1_q_a[7]_PORT_B_address_reg = DFFE(H1_q_a[7]_PORT_B_address, H1_q_a[7]_clock_1, , , );
H1_q_a[7]_PORT_A_write_enable = WREN;
H1_q_a[7]_PORT_A_write_enable_reg = DFFE(H1_q_a[7]_PORT_A_write_enable, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_PORT_B_write_enable = J1L23;
H1_q_a[7]_PORT_B_write_enable_reg = DFFE(H1_q_a[7]_PORT_B_write_enable, H1_q_a[7]_clock_1, , , );
H1_q_a[7]_clock_0 = GLOBAL(D1L1);
H1_q_a[7]_clock_1 = GLOBAL(A1L7);
H1_q_a[7]_PORT_A_data_out = MEMORY(H1_q_a[7]_PORT_A_data_in_reg, H1_q_a[7]_PORT_B_data_in_reg, H1_q_a[7]_PORT_A_address_reg, H1_q_a[7]_PORT_B_address_reg, H1_q_a[7]_PORT_A_write_enable_reg, H1_q_a[7]_PORT_B_write_enable_reg, , , H1_q_a[7]_clock_0, H1_q_a[7]_clock_1, , , , );
H1_q_a[4] = H1_q_a[7]_PORT_A_data_out[3];

--H1_q_a[5] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|altsyncram_3fb2:altsyncram1|q_a[5] at M4K_X17_Y7
H1_q_a[7]_PORT_A_data_in = BUS(B1_REGL[7], B1_REGL[6], B1_REGL[5], B1_REGL[4], B1_REGL[3], B1_REGL[2], B1_REGL[1], B1_REGL[0]);
H1_q_a[7]_PORT_A_data_in_reg = DFFE(H1_q_a[7]_PORT_A_data_in, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_PORT_B_data_in = BUS(J1_ram_rom_data_reg[7], J1_ram_rom_data_reg[6], J1_ram_rom_data_reg[5], J1_ram_rom_data_reg[4], J1_ram_rom_data_reg[3], J1_ram_rom_data_reg[2], J1_ram_rom_data_reg[1], J1_ram_rom_data_reg[0]);
H1_q_a[7]_PORT_B_data_in_reg = DFFE(H1_q_a[7]_PORT_B_data_in, H1_q_a[7]_clock_1, , , );
H1_q_a[7]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8]);
H1_q_a[7]_PORT_A_address_reg = DFFE(H1_q_a[7]_PORT_A_address, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_PORT_B_address = BUS(M1_safe_q[0], M1_safe_q[1], M1_safe_q[2], M1_safe_q[3], M1_safe_q[4], M1_safe_q[5], M1_safe_q[6], M1_safe_q[7], M1_safe_q[8]);
H1_q_a[7]_PORT_B_address_reg = DFFE(H1_q_a[7]_PORT_B_address, H1_q_a[7]_clock_1, , , );
H1_q_a[7]_PORT_A_write_enable = WREN;
H1_q_a[7]_PORT_A_write_enable_reg = DFFE(H1_q_a[7]_PORT_A_write_enable, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_PORT_B_write_enable = J1L23;
H1_q_a[7]_PORT_B_write_enable_reg = DFFE(H1_q_a[7]_PORT_B_write_enable, H1_q_a[7]_clock_1, , , );
H1_q_a[7]_clock_0 = GLOBAL(D1L1);
H1_q_a[7]_clock_1 = GLOBAL(A1L7);
H1_q_a[7]_PORT_A_data_out = MEMORY(H1_q_a[7]_PORT_A_data_in_reg, H1_q_a[7]_PORT_B_data_in_reg, H1_q_a[7]_PORT_A_address_reg, H1_q_a[7]_PORT_B_address_reg, H1_q_a[7]_PORT_A_write_enable_reg, H1_q_a[7]_PORT_B_write_enable_reg, , , H1_q_a[7]_clock_0, H1_q_a[7]_clock_1, , , , );
H1_q_a[5] = H1_q_a[7]_PORT_A_data_out[2];

--H1_q_a[6] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|altsyncram_3fb2:altsyncram1|q_a[6] at M4K_X17_Y7
H1_q_a[7]_PORT_A_data_in = BUS(B1_REGL[7], B1_REGL[6], B1_REGL[5], B1_REGL[4], B1_REGL[3], B1_REGL[2], B1_REGL[1], B1_REGL[0]);
H1_q_a[7]_PORT_A_data_in_reg = DFFE(H1_q_a[7]_PORT_A_data_in, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_PORT_B_data_in = BUS(J1_ram_rom_data_reg[7], J1_ram_rom_data_reg[6], J1_ram_rom_data_reg[5], J1_ram_rom_data_reg[4], J1_ram_rom_data_reg[3], J1_ram_rom_data_reg[2], J1_ram_rom_data_reg[1], J1_ram_rom_data_reg[0]);
H1_q_a[7]_PORT_B_data_in_reg = DFFE(H1_q_a[7]_PORT_B_data_in, H1_q_a[7]_clock_1, , , );
H1_q_a[7]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8]);
H1_q_a[7]_PORT_A_address_reg = DFFE(H1_q_a[7]_PORT_A_address, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_PORT_B_address = BUS(M1_safe_q[0], M1_safe_q[1], M1_safe_q[2], M1_safe_q[3], M1_safe_q[4], M1_safe_q[5], M1_safe_q[6], M1_safe_q[7], M1_safe_q[8]);
H1_q_a[7]_PORT_B_address_reg = DFFE(H1_q_a[7]_PORT_B_address, H1_q_a[7]_clock_1, , , );
H1_q_a[7]_PORT_A_write_enable = WREN;
H1_q_a[7]_PORT_A_write_enable_reg = DFFE(H1_q_a[7]_PORT_A_write_enable, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_PORT_B_write_enable = J1L23;
H1_q_a[7]_PORT_B_write_enable_reg = DFFE(H1_q_a[7]_PORT_B_write_enable, H1_q_a[7]_clock_1, , , );
H1_q_a[7]_clock_0 = GLOBAL(D1L1);
H1_q_a[7]_clock_1 = GLOBAL(A1L7);
H1_q_a[7]_PORT_A_data_out = MEMORY(H1_q_a[7]_PORT_A_data_in_reg, H1_q_a[7]_PORT_B_data_in_reg, H1_q_a[7]_PORT_A_address_reg, H1_q_a[7]_PORT_B_address_reg, H1_q_a[7]_PORT_A_write_enable_reg, H1_q_a[7]_PORT_B_write_enable_reg, , , H1_q_a[7]_clock_0, H1_q_a[7]_clock_1, , , , );
H1_q_a[6] = H1_q_a[7]_PORT_A_data_out[1];

--H1_q_b[0] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|altsyncram_3fb2:altsyncram1|q_b[0] at M4K_X17_Y7
H1_q_b[7]_PORT_A_data_in = BUS(B1_REGL[7], B1_REGL[6], B1_REGL[5], B1_REGL[4], B1_REGL[3], B1_REGL[2], B1_REGL[1], B1_REGL[0]);
H1_q_b[7]_PORT_A_data_in_reg = DFFE(H1_q_b[7]_PORT_A_data_in, H1_q_b[7]_clock_0, , , );
H1_q_b[7]_PORT_B_data_in = BUS(J1_ram_rom_data_reg[7], J1_ram_rom_data_reg[6], J1_ram_rom_data_reg[5], J1_ram_rom_data_reg[4], J1_ram_rom_data_reg[3], J1_ram_rom_data_reg[2], J1_ram_rom_data_reg[1], J1_ram_rom_data_reg[0]);
H1_q_b[7]_PORT_B_data_in_reg = DFFE(H1_q_b[7]_PORT_B_data_in, H1_q_b[7]_clock_1, , , );
H1_q_b[7]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8]);
H1_q_b[7]_PORT_A_address_reg = DFFE(H1_q_b[7]_PORT_A_address, H1_q_b[7]_clock_0, , , );
H1_q_b[7]_PORT_B_address = BUS(M1_safe_q[0], M1_safe_q[1], M1_safe_q[2], M1_safe_q[3], M1_safe_q[4], M1_safe_q[5], M1_safe_q[6], M1_safe_q[7], M1_safe_q[8]);
H1_q_b[7]_PORT_B_address_reg = DFFE(H1_q_b[7]_PORT_B_address, H1_q_b[7]_clock_1, , , );
H1_q_b[7]_PORT_A_write_enable = WREN;
H1_q_b[7]_PORT_A_write_enable_reg = DFFE(H1_q_b[7]_PORT_A_write_enable, H1_q_b[7]_clock_0, , , );
H1_q_b[7]_PORT_B_write_enable = J1L23;
H1_q_b[7]_PORT_B_write_enable_reg = DFFE(H1_q_b[7]_PORT_B_write_enable, H1_q_b[7]_clock_1, , , );
H1_q_b[7]_clock_0 = GLOBAL(D1L1);
H1_q_b[7]_clock_1 = GLOBAL(A1L7);
H1_q_b[7]_PORT_B_data_out = MEMORY(H1_q_b[7]_PORT_A_data_in_reg, H1_q_b[7]_PORT_B_data_in_reg, H1_q_b[7]_PORT_A_address_reg, H1_q_b[7]_PORT_B_address_reg, H1_q_b[7]_PORT_A_write_enable_reg, H1_q_b[7]_PORT_B_write_enable_reg, , , H1_q_b[7]_clock_0, H1_q_b[7]_clock_1, , , , );
H1_q_b[0] = H1_q_b[7]_PORT_B_data_out[7];

--H1_q_b[1] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|altsyncram_3fb2:altsyncram1|q_b[1] at M4K_X17_Y7
H1_q_b[7]_PORT_A_data_in = BUS(B1_REGL[7], B1_REGL[6], B1_REGL[5], B1_REGL[4], B1_REGL[3], B1_REGL[2], B1_REGL[1], B1_REGL[0]);
H1_q_b[7]_PORT_A_data_in_reg = DFFE(H1_q_b[7]_PORT_A_data_in, H1_q_b[7]_clock_0, , , );
H1_q_b[7]_PORT_B_data_in = BUS(J1_ram_rom_data_reg[7], J1_ram_rom_data_reg[6], J1_ram_rom_data_reg[5], J1_ram_rom_data_reg[4], J1_ram_rom_data_reg[3], J1_ram_rom_data_reg[2], J1_ram_rom_data_reg[1], J1_ram_rom_data_reg[0]);
H1_q_b[7]_PORT_B_data_in_reg = DFFE(H1_q_b[7]_PORT_B_data_in, H1_q_b[7]_clock_1, , , );
H1_q_b[7]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8]);
H1_q_b[7]_PORT_A_address_reg = DFFE(H1_q_b[7]_PORT_A_address, H1_q_b[7]_clock_0, , , );
H1_q_b[7]_PORT_B_address = BUS(M1_safe_q[0], M1_safe_q[1], M1_safe_q[2], M1_safe_q[3], M1_safe_q[4], M1_safe_q[5], M1_safe_q[6], M1_safe_q[7], M1_safe_q[8]);
H1_q_b[7]_PORT_B_address_reg = DFFE(H1_q_b[7]_PORT_B_address, H1_q_b[7]_clock_1, , , );
H1_q_b[7]_PORT_A_write_enable = WREN;
H1_q_b[7]_PORT_A_write_enable_reg = DFFE(H1_q_b[7]_PORT_A_write_enable, H1_q_b[7]_clock_0, , , );
H1_q_b[7]_PORT_B_write_enable = J1L23;
H1_q_b[7]_PORT_B_write_enable_reg = DFFE(H1_q_b[7]_PORT_B_write_enable, H1_q_b[7]_clock_1, , , );
H1_q_b[7]_clock_0 = GLOBAL(D1L1);
H1_q_b[7]_clock_1 = GLOBAL(A1L7);
H1_q_b[7]_PORT_B_data_out = MEMORY(H1_q_b[7]_PORT_A_data_in_reg, H1_q_b[7]_PORT_B_data_in_reg, H1_q_b[7]_PORT_A_address_reg, H1_q_b[7]_PORT_B_address_reg, H1_q_b[7]_PORT_A_write_enable_reg, H1_q_b[7]_PORT_B_write_enable_reg, , , H1_q_b[7]_clock_0, H1_q_b[7]_clock_1, , , , );
H1_q_b[1] = H1_q_b[7]_PORT_B_data_out[6];

--H1_q_b[2] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|altsyncram_3fb2:altsyncram1|q_b[2] at M4K_X17_Y7
H1_q_b[7]_PORT_A_data_in = BUS(B1_REGL[7], B1_REGL[6], B1_REGL[5], B1_REGL[4], B1_REGL[3], B1_REGL[2], B1_REGL[1], B1_REGL[0]);
H1_q_b[7]_PORT_A_data_in_reg = DFFE(H1_q_b[7]_PORT_A_data_in, H1_q_b[7]_clock_0, , , );
H1_q_b[7]_PORT_B_data_in = BUS(J1_ram_rom_data_reg[7], J1_ram_rom_data_reg[6], J1_ram_rom_data_reg[5], J1_ram_rom_data_reg[4], J1_ram_rom_data_reg[3], J1_ram_rom_data_reg[2], J1_ram_rom_data_reg[1], J1_ram_rom_data_reg[0]);
H1_q_b[7]_PORT_B_data_in_reg = DFFE(H1_q_b[7]_PORT_B_data_in, H1_q_b[7]_clock_1, , , );
H1_q_b[7]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8]);