adcint.bsf

基于fpga和sopc的用VHDL语言编写的EDA的ADC0809采样控制电路

/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
*/
(header "symbol" (version "1.1"))
(symbol
	(rect 16 16 136 176)
	(text "ADCINT" (rect 5 0 46 12)(font "Arial" ))
	(text "inst" (rect 8 144 25 156)(font "Arial" ))
	(port
		(pt 0 32)
		(input)
		(text "D[7..0]" (rect 0 0 34 12)(font "Arial" ))
		(text "D[7..0]" (rect 21 27 55 39)(font "Arial" ))
		(line (pt 0 32)(pt 16 32)(line_width 3))
	)
	(port
		(pt 0 48)
		(input)
		(text "CLK" (rect 0 0 21 12)(font "Arial" ))
		(text "CLK" (rect 21 43 42 55)(font "Arial" ))
		(line (pt 0 48)(pt 16 48)(line_width 1))
	)
	(port
		(pt 0 64)
		(input)
		(text "EOC" (rect 0 0 23 12)(font "Arial" ))
		(text "EOC" (rect 21 59 44 71)(font "Arial" ))
		(line (pt 0 64)(pt 16 64)(line_width 1))
	)
	(port
		(pt 120 32)
		(output)
		(text "ALE" (rect 0 0 20 12)(font "Arial" ))
		(text "ALE" (rect 79 27 99 39)(font "Arial" ))
		(line (pt 120 32)(pt 104 32)(line_width 1))
	)
	(port
		(pt 120 48)
		(output)
		(text "START" (rect 0 0 34 12)(font "Arial" ))
		(text "START" (rect 65 43 99 55)(font "Arial" ))
		(line (pt 120 48)(pt 104 48)(line_width 1))
	)
	(port
		(pt 120 64)
		(output)
		(text "OE" (rect 0 0 15 12)(font "Arial" ))
		(text "OE" (rect 84 59 99 71)(font "Arial" ))
		(line (pt 120 64)(pt 104 64)(line_width 1))
	)
	(port
		(pt 120 80)
		(output)
		(text "ADDA" (rect 0 0 30 12)(font "Arial" ))
		(text "ADDA" (rect 69 75 99 87)(font "Arial" ))
		(line (pt 120 80)(pt 104 80)(line_width 1))
	)
	(port
		(pt 120 96)
		(output)
		(text "LOCK0" (rect 0 0 35 12)(font "Arial" ))
		(text "LOCK0" (rect 64 91 99 103)(font "Arial" ))
		(line (pt 120 96)(pt 104 96)(line_width 1))
	)
	(port
		(pt 120 112)
		(output)
		(text "Q[7..0]" (rect 0 0 34 12)(font "Arial" ))
		(text "Q[7..0]" (rect 65 107 99 119)(font "Arial" ))
		(line (pt 120 112)(pt 104 112)(line_width 3))
	)
	(drawing
		(rectangle (rect 16 16 104 144)(line_width 1))
	)
)