📄 examplesa.txt
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case ({a, b, c})
3'b001: f = 1'b1;
3'b010: f = 1'b1;
3'b011: f = 1'b1;
3'b100: f = 1'b1;
3'b110: f = 1'b0;
3'b111: f = 1'b1;
default: f = 1'bx;
endcase
endmodule
//example 6.7
module synUsingDC (f, a, b);
output f;
input a, b;
reg f;
always @(a or b)
casex ({a, b})
2'b0?: f = 1;
2'b10: f = 0;
2'b11: f = 1;
endcase
endmodule
//example 6.8
module synXor8 (xout, xin1, xin2);
output [1:8] xout;
input [1:8] xin1, xin2;
reg [1:8] xout, i;
always @(xin1 or xin2)
for (i = 1; i <= 8; i = i + 1)
xout[i] = xin1[i] ^ xin2[i];
endmodule
//example 6.9
module synLatchReset (Q, g, d, reset);
output Q;
input g, d, reset;
reg Q;
always @(g or d or reset)
if (~reset)
Q = 0;
else if (g)
Q = d;
endmodule
//example 6.10
module synDFF (q, d, clock);
output q;
input clock, d;
reg q;
always @(negedge clock)
q <= d;
endmodule
//example 6.11
module synDFFwithSetReset (q, d, reset, set, clock);
input d, reset, set, clock;
output q;
reg q;
always @(posedge clock or negedge reset or posedge set) begin
if (~reset)
q <= 0;
else if (set)
q <= 1;
else q <= d;
end
endmodule
//example 6.12
module synTriState (bus, in, driveEnable);
input in, driveEnable;
output bus;
reg bus;
always @(in or driveEnable)
if (driveEnable)
bus = in;
else bus = 1'bz;
endmodule
//example 6.13
module fsm (i, clock, reset, out);
input i, clock, reset;
output [2:0] out;
reg [2:0] out;
reg [2:0] currentState, nextState;
parameter [2:0] A = 0, // The state
labels and their assignments
B = 1,
C = 2,
D = 3,
E = 4,
F = 5;
always @(i or currentState)
// The combinational logic
case (currentState)
A: begin
nextState = (i == 0) ? A : B;
out = (i == 0) ? 3'b000 : 3'b100;
end
B: begin
nextState = (i == 0) ? A : C;
out = (i == 0) ? 3'b000 : 3'b100;
end
C: begin
nextState = (i == 0) ? A : D;
out = (i == 0) ? 3'b000 : 3'b101;
end
D: begin
nextState = (i == 0) ? D : E;
out = (i == 0) ? 3'b010 : 3'b110;
end
E: begin
nextState = (i == 0) ? D : F;
out = (i == 0) ? 3'b010 : 3'b110;
end
F: begin
nextState = D;
out = (i == 0) ? 3'b000 : 3'b101;
end
default: begin // oops, undefined
states. Go to state A
nextState = A;
out = (i == 0) ? 3'bxxx : 3'bxxx;
end
endcase
always @(posedge clock or negedge reset) // The state register
if (~reset)
currentState <= A;
else
currentState <= nextState;
endmodule
//example 6.14
module synImplicit (dataIn, dataOut, c1, c2, clock);
input [7:0] dataIn, c1, c2;
input clock;
output [7:0] dataOut;
reg [7:0] dataOut, temp;
always begin
@ (posedge clock)
temp = dataIn + c1;
@ (posedge clock)
temp = temp & c2;
@ (posedge clock)
dataOut = temp - c1;
end
endmodule
//example 6.15
module synPipe (dataIn, dataOut, c1, c2, clock);
input [7:0] dataIn, c1, c2;
input clock;
output [7:0] dataOut;
reg [7:0] dataOut;
reg [7:0] stageOne;
reg [7:0] stageTwo;
always @ (posedge clock)
stageOne <= dataIn + c1;
always @ (posedge clock)
stageTwo <= stageOne & c2;
always @ (posedge clock)
dataOut <= stageTwo + stageOne;
endmodule
//example 6.16
module synSwitchFilter (Clock, reset, in, switch, out);
input Clock, reset, switch;
input [7:0] in;
output [7:0] out;
reg [7:0] out, x1, x2, x3, y, yold, delta;
initial forever @(negedge reset) begin
disable main;
out = 0;
y = 1;
x2 = 2;
x3 = 3;
end
always begin :main)
wait (reset);
@(posedge Clock)
x1 = in;
out <= y;
yold = y;
y = x1 + x2 + x3;
delta = y - yold;
delta = delta >> 1;
if (switch == 1) begin
delta = delta >> 1;
@(posedge Clock) out <= out + delta;
@(posedge Clock) out <= out + delta;
end
@(posedge Clock) out <= out + delta;
x3 = x2;
x2 = x1;
end
endmodule
//example 6.17
primitive carry(carryOut, carryIn, aIn, bIn);
output carryOut;
input carryIn,
aIn,
bIn;
table
0 00 : 0;
0 01 : 0;
0 10 : 0;
0 11 : 1;
1 00 : 0;
1 01 : 1;
1 10 : 1;
1 11 : 1;
endtable
endprimitive
//example 7.1
primitive carryX(carryOut, carryIn, aIn, bIn);
output carryOut;
input aIn,
bIn,
carryIn;
table
0 00 : 0;
0 01 : 0;
0 10 : 0;
0 11 : 1;
1 00 : 0;
1 01 : 1;
1 10 : 1;
1 11 : 1;
0 0x : 0;
0 x0 : 0;
x 00 : 0;
1 1x : 1;
1 x1 : 1;
x 11 : 1;
endtable
endprimitive
//example 7.2
primitive carryAbbrev (carryOut, carryIn, aIn, bIn);
output carryOut;
input aIn,
bIn,
carryIn;
table
0 0? : 0;
0 ?0 : 0;
? 00 : 0;
? 11 : 1;
1 ?1 : 1;
1 1? : 1;
endtable
endprimitive
//example 7.3
primitive latch (q, clock, data);
output q;
reg q;
input clock, data;
table
// clock data state output
0 1 : ? : 1;
0 0 : ? : 0;
1 ? : ? : -;
endtable
endprimitive
//example 7.4
primitive dEdgeFF (q, clock, data);
output q;
reg q;
input clock, data;
table
// clock data state output
(01) 0 : ? :
0;
(01) 1 : ? : 1;
(0x) 1 : 1 : 1;
(0x) 0 : 0 : 0;
(?0) ? : ? : -;
? (??) : ? : -;
endtable
endprimitive
//example 7.5
primitive dEdgeFFShort (q, clock, data);
output q;
reg q;
input clock, data;
table
// clock data state output
r 0 : ? : 0;
r 1 : ? : 1;
(0x) 0 : 1 : 1;
(0x) 1 : 1 : 1;
(?0) ? : ? : -;
? * : ? : -;
endtable
endprimitive
//example 7.6
primitive jkEdgeFF (q, clock, j, k, preset, clear);
output q;
reg q;
input clock, j, k, preset, clear;
table
//clock jk pc state output
// preset logic
? ?? 01 : ? : 1;
? ?? *1 : 1 : 1;
// clear logic
? ?? 10 : ? : 0;
? ?? 1* : 0 : 0;
// normal clocking cases
r 00 11 : ? : -;
r 01 11 : ? : 0;
r 10 11 : ? : 1;
r 11 11 : 0 : 1;
r 11 11 : 1 : 0;
f ?? ?? : ? : -;
// j and k transition cases
b *? ?? : ? : -;
b ?* ?? : ? : -;
//cases reducing pessimism
p 00 11 : ? : -;
p 0? 1? : 0 : -;
p ?0 ?1 : 1 : -;
(x0) ?? ?? : ? : -;
(1x) 00 11 : ? : -;
(1x) 0? 1? : 0 : -;
(1x) ?0 ?1 : 1 : -;
x *0 ?1 : 1 : -;
x 0* 1? : 0 : -;
endtable
endprimitive
//example 7.7
module shreg (out, in, phase1, phase2);
/* IO port declarations, where 'out' is the inverse
of 'in' controlled by the dual-phased clock */
output out; //shift register output
input in, //shift register input
phase1, //clocks
phase2;
tri wb1, wb2, out; //tri nets
pulled up to VDD
pullup (wb1), (wb2), (out);
//depletion mode pullup devices
trireg (medium) wa1, wa2, wa3 ;
//charge storage nodes
supply0 gnd; //ground supply
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