examplesa.txt

熟悉verilog,帮助初学者尽快掌握verilog

initial         enable = 0;

always           // bus master end
        begin
                wiggleBusLines (`READ, 2, 0);
                wiggleBusLines (`READ, 3, 0);
                wiggleBusLines (`WRITE, 2, 5);
                wiggleBusLines (`WRITE, 3, 7);
                wiggleBusLines (`READ, 2, 0);
                wiggleBusLines (`READ, 3, 0);
                $finish;
        end

task wiggleBusLines;
input                                   readWrite;
input           [Asize:0]                       addr;
input           [Dsize:0]                       data;

        begin
                #Tprop
                rw = readWrite;
                if (rw) begin                           // write value
                        addressLines = addr;
                        internalData = data;
                        enable = 1;
                end
                else begin                              //read value
                        addressLines = addr;
                        @ (negedge clock);
                end
                @(negedge clock);
                enable = 0;
        end
endtask
endmodule

module busDriver(busLine, valueToGo, driveEnable);
parameter
        Bsize = 15;
inout           [Bsize:0]                       busLine;
input           [Bsize:0]                       valueToGo;
input                                   driveEnable;

        assign busLine = (driveEnable) ? valueToGo: 'bz;
endmodule
//example 4.12




module triStateLatch (qOut, nQOut, clock, data, enable);
output          qOut, nQOut;
input           clock, data, enable;
tri             qOut, nQOut;

        not             #5                              (ndata, data);
        nand            #(3,5)                          d(wa, data, clock),
                                                        nd(wb, ndata, clock);
        nand            #(12, 15)                               qQ(q, nq, wa),
                                                        nQ(nq, q, wb);
        bufif1          #(3, 7, 13)                             qDrive (qOut, q, 
enable),
                                                        nQDrive(nQOut, nq, 
enable);
endmodule
//example 4.13




module IOBuffer (bus, in, out, dir);
inout           bus;
input           in, dir;
output          out;

parameter
        R_Min = 3, R_Typ = 4, R_Max = 5,
        F_Min = 3, F_Typ = 5, F_Max = 7,
        Z_Min = 12, Z_Typ = 15, Z_Max = 17;

        bufif1          #(R_Min: R_Typ: R_Max, 
                                        F_Min: F_Typ: F_Max,
                                        Z_Min: Z_Typ: Z_Max)
                        (bus, out, dir);

        buf             #(R_Min: R_Typ: R_Max, 
                                        F_Min: F_Typ: F_Max)
                        (in, bus);
endmodule
//example 4.14
module dEdgeFF (clock, d, clear, preset, q);
input           clock, d, clear, preset;
output          q;

        specify
                // specify parameters
                specparam                       tRiseClkQ       = 100,
                                        tFallClkQ       = 120,
                                        tRiseCtlQ        = 50,
                                        tFallCtlQ        = 60;

                // module path declarations
                (clock => q) = (tRiseClkQ, tFallClkQ);
                (clear, preset *> q) = (tRiseCtlQ, tFallCtlQ);
        endspecify

        // description of module's internals
endmodule
//example 4.15



module behavioralNand (out, in1, in2, in3);
        output                  out;
        input                   in1, in2, in3;
        parameter                       delay = 5;

        always
                @ (in1 or in2 or in3)
                        #delay out = ~(in1 & in2 & in3);
endmodule
   /example 5.3



module twoPhiLatch (phi1, phi2, q, d);
        input           phi1, phi2, d;
        output          q;
        reg             q, qInternal;

        always begin
                @ (posedge phi1)
                        qInternal = d;
                @ (posedge phi2)
                        q = qInternal;
        end
endmodule
//example 5.4



module twoPhiLatchWithDelay (phi1, phi2, q, d);
        input           phi1, phi2, d;
        output          q;
        reg             q, qInternal;

        always begin
                @ (posedge phi1)
                        #2 qInternal = d;
                @ (posedge phi2)
                        #2 q = qInternal;
        end
endmodule
//example 5.5





module stupidVerilogTricks (f, a, b);
        input           a, b;
        output          f;
        reg             f, q;

        initial
                f = 0;

        always
                @ (posedge a)
                        #10 q = b;

        always
                @ q
                        f = qBar;

        not             (qBar, q);

endmodule
//example 5.6



module goesBothWays (Q, clock);
        input                           clock;
        output          [2:1]           Q;

        wire            Q[1] = q1,
                        Q[2] = q2;

        dff             a (q1, ~q1, clock),
                        b (q2, q1, clock);
endmodule

module dff (q, d, clock);
        input           d, clock;
        output          q;

        always
                @(posedge clock)
                        #3 q = d;
endmodule
//example 5.8



module suspend;
        reg             a;
        wire            b = a;

        initial begin
                a = 1;
                $display ("a = %b, b = %b", a, b);
        end
endmodule
//example 5.9



module inertialNand (doneIt, lisa, michael);
        output                  doneIt;
        input                   lisa, 
                                michael;
        reg                     doneIt;
        parameter                       pDelay = 5;

        always
                @(lisa or michael)
                        doneIt <= #pDelay lisa ~& michael;
endmodule
//example 5.10






module pipeMult (product, mPlier, mCand, go, clock);
        input                           go, clock;
        input           [9:0]           mPlier, mCand;
        output          [19:0]          product;
        reg             [19:0]          product;

        always
                @(posedge go)
                        product <= repeat (4) @(posedge clock) mPlier * mCand;
endmodule
//example 5.11



module sMux (f, a, b, select);
        input           a, b, select;
        output          f;

        nand            #8
                (f, aSelect, bSelect),
                (aSelect, select, a),
                (bSelect, notSelect, b);
        not             
                (notSelect, select);
endmodule
//examples 5.p1





module bMux (f, a, b, select);
        input           a, b, select;
        output          f;
        reg             f;

        always
                @select
                         #8 f = (select) ? a : b;
endmodule
//examples 5.p2





module beenThere;
        reg             [15:0]          q;
        wire                            h, addit;

        doneThat (q, h, addit);
        initial q = 20;

        always begin
                wait (posedge h);
                if (addit == 1)
                        q = q + 5;
                else    q = q - 3;
        end
endmodule
//example 5.p3




module doneThat(que, f, add);
        input           [15:0]          que;
        output                          f, add;
        reg                             f, add;
        always
                #10 f = ~ f;

        initial begin
                f = 0;
                add = 0;
                #14 add = que + 1;
                #14 add = 0;
        end
endmodule
//example 5.p4

module synGate (f, a, b, c);
        output          f;
        input           a, b, c;

        and             A (a1, a, b, c);
        and             B (a2, a, ~b, ~c);
        and             C (a3, ~a, o1);
        or              D (o1, b, c);
        or              E (f, a1, a2, a3);
endmodule
//example 6.1





module synAssign (f, a, b, c);
        output          f;
        input           a, b, c;

        assign          f = (a & b & c) | (a & ~b & ~c) | (~a & (b | c));
endmodule
//example 6.2








module synCombinationalAlways (f, a, b, c);
        output          f;
        input           a, b, c;
        reg             f;

        always @ (a or b or c)
                if (a == 1)
                        f = b;
                else
                        f = c;
endmodule
//example 6.3







module synInferredLatch (f, a, b, c);
        output          f;
        input           a, b, c;
        reg             f;

        always @(a or b or c)
                if (a == 1)
                        f = b & c;
endmodule
//example 6.4





module synCase (f, a, b, c);
        output          f;
        input           a, b, c;
        reg             f;

        always @(a or b or c)
                case ({a, b, c})
                        3'b000:                 f = 1'b0;
                        3'b001:                 f = 1'b1;
                        3'b010:                 f = 1'b1;
                        3'b011:                 f = 1'b1;
                        3'b100:                 f = 1'b1;
                        3'b101:                 f = 1'b0;
                        3'b110:                 f = 1'b0;
                        3'b111:                 f = 1'b1;
                endcase
endmodule
//example 6.5








module synCaseWithDefault (f, a, b, c);
        output          f;
        input           a, b, c;
        reg             f;

        always @(a or b or c)
                case ({a, b, c})
                        3'b000:                 f = 1'b0;
                        3'b101:                 f = 1'b0;
                        3'b110:                 f = 1'b0;
                        default:                        f = 1'b1;
                endcase
endmodule
//example 6.6







module synCaseWithDC (f, a, b, c);
        output          f;
        input           a, b, c;
        reg             f;

        always @(a or b or c)