examplesa.txt

熟悉verilog,帮助初学者尽快掌握verilog

//read
                        #tProp dataLines = m[addressLines];
                        @(negedge clock);
                end
                else            //write
                        m[addressLines] = dataLines;
        end
endmodule
//example 3.10




module numberGenDisable (number, reset);
        output          [15:0]          number;
        input                           reset;
        event                           ready;
        reg             [15:0]          number;

        always
                begin :generator
                        number = 3;
                        forever
                                begin
                                        #100 number = number + 1;
                                        -> ready;
                                end
                end

        always
                @(negedge reset) disable generator;
endmodule
//example 3.11




module dFlop (preset, clear, q, clock, d);
        input           preset, clear, clock, d;
        output          q;
        reg             q;

        always 
                @(clear or preset)
                        begin
                                if (!clear)
                                        #10             assign q = 0;
                                else if (!preset)
                                        #10             assign q = 1;
                                else
                                        #10             deassign q;
                        end

        always 
                @(negedge clock)
                        #10     q = d;
endmodule
//example 3.12
module numberGenFork (number, reset);
        output          [15:0]          number;
        input                           reset;
        event                           ready;
        reg             [15:0]          number;

        always
                begin 
                        number = 0;
                        fork : generator
                                forever
                                        begin
                                                #50 number = number + 1;
                                                #50 -> ready;
                                        end
                                @(negedge reset) 
                                        disable generator;
                        join
                end
endmodule
//example 3.14




module fullAdder(cOut, sum, aIn, bIn, cIn);
        output          cOut, sum;
        input           aIn, bIn, cIn;

        wire            x2;

        nand            (x2, aIn, bIn),
                        (cOut, x2, x8);
        xnor            (x9, x5, x6);
        nor             (x5, x1, x3),
                        (x1, aIn, bIn);
        or              (x8, x1, x7);
        not             (sum, x9),
                        (x3, x2),
                        (x6, x4),
                        (x4, cIn),
                        (x7, x6);
endmodule
//example 4.1




module andOfComplements (a, b, c, d);
input           a, b;
output          c, d;

wand            c;
wire            d;

        not     (c, a);
        not     (c, b);

        not     (d, a);
        not     (d, b);
endmodule
//example 4.2
module ace;
        wire            r, t;
        reg             q, s;
                // other declarations

        andOfComplements                                                m1 
(.b(s), .a(q), .c(r), .d(t));
endmodule//example 4.2ace




module testHam();

reg             [1:8]            original;
wire            [1:8]           regenerated;
wire            [1:12]          encoded,
                                messedUp;
integer                         seed;

        initial begin
                seed = 1;
                forever begin
                        original = $random (seed);
                        #1 
                        $display ("original=%h, encoded=%h, messed=%h,regen=%h",
                                                original, encoded, messedUp, 
regenerated);
                end
        end

        hamEncode hIn (original, encoded);
        hamDecode hOut(messedUp, regenerated);
        
        assign messedUp = encoded ^ 12'b 0000_0010_0000;
endmodule


module hamEncode (vIn, valueOut);
input           [1:8]           vIn;
output          [1:12]          valueOut;

wire            h1, h2, h4, h8;

        xor             (h1, vIn[1], vIn[2], vIn[4], vIn[5], vIn[7]),
                        (h2, vIn[1], vIn[3], vIn[4], vIn[6], vIn[7]),
                        (h4, vIn[2], vIn[3], vIn[4], vIn[8]),
                        (h8, vIn[5], vIn[6], vIn[7], vIn[8]);

        assign valueOut = {h1, h2, vIn[1], h4, vIn[2:4], h8, vIn[5:8]};

endmodule

module hamDecode (vIn, valueOut);
input           [1:12]          vIn;
output          [1:8]           valueOut;
wire            c1, c2, c4, c8;
wire            [1:8]            bitFlippers;
        xor             (c1, vIn[1], vIn[3], vIn[5], vIn[7], vIn[9], vIn[11]),
                        (c2, vIn[2], vIn[3], vIn[6], vIn[7], vIn[10], vIn[11]),
                        (c4, vIn[4], vIn[5], vIn[6], vIn[7], vIn[12]),
                        (c8, vIn[8], vIn[9], vIn[10], vIn[11], vIn[12]);

        deMux mux1 (bitFlippers, c1, c2, c4, c8, 1'b1);
        xor8 x1 (valueOut, bitFlippers, {vIn[3], vIn[5], vIn[6], vIn[7], vIn[9], vIn[10
], vIn[11], vIn[12]});
endmodule

module deMux (outVector, a, b, c, d, enable);
output           [1:8]           outVector;
input                           a, b, c, d, enable;
        and             (m12, d, c, ~b, ~a, enable),
                        (m11, d, ~c, b, a, enable),
                        (m10, d, ~c, b, ~a, enable),
                        (m9, d, ~c, ~b, a, enable),
                        (m7, ~d, c, b, a, enable),
                        (m6, ~d, c, b, ~a, enable),
                        (m5, ~d, c, ~b, a, enable),
                        (m3, ~d, ~c, b, a, enable);

        assign outVector = {m3, m5, m6, m7, m9, m10, m11, m12};
endmodule

module xor8 (xout, xin1, xin2);
output          [1:8]           xout;
input           [1:8]           xin1, xin2;
        xor             (xout[8], xin1[8], xin2[8]),
                        (xout[7], xin1[7], xin2[7]),
                        (xout[6], xin1[6], xin2[6]),
                        (xout[5], xin1[5], xin2[5]),
                        (xout[4], xin1[4], xin2[4]),
                        (xout[3], xin1[3], xin2[3]),
                        (xout[2], xin1[2], xin2[2]),
                        (xout[1], xin1[1], xin2[1]);
endmodule
//example 4.3




module oneBitFullAdder(cOut, sum, aIn, bIn, cIn);
output          cOut, sum;
input           aIn, bIn, cIn;

assign                  sum = aIn ^ bIn ^ cIn,
                        cOut = (aIn & bIn) | (bIn & cIn) | (aIn & cIn);

endmodule
//example 4.4




module multiplexor(a, b, c, d, select, e);
input                   a, b, c, d;
input           [1:0]   select;
output                  e;

        assign          e = mux (a, b, c, d, select);

function         mux;
input                   a, b, c, d;
input           [1:0]   select;

        case (select)
                2'b00:          mux = a;
                2'b01:          mux = b;
                2'b10:          mux = c;
                2'b11:          mux = d;
                default:                mux = 'bx;
        endcase
endfunction

endmodule
//example 4.5
module modXor (AXorB, a, b);
        output          [7:0]           AXorB;
        input           [7:0]           a, b;

        wire            [7:0]           #5 AXorB = a ^ b;
endmodule
//example 4.6
module wandOfAssigns (a, b, c);
input           a, b;
output          c;

        wand            #10             c;

        assign          #5      c = ~a;
        assign          #3      c = ~b;
endmodule
//example 4.7




module bufferDriver (busLine, bufferedVal, bufInput, busEnable);
inout           busLine;
input           bufInput, busEnable;
output          bufferedVal;

        assign          bufferedVal = busLine,
                        busLine = (busEnable) ? bufInput : 1'bz;
endmodule
//example 4.8




module xor8 (xout, xin1, xin2);
output          [1:8]           xout;
input           [1:8]           xin1, xin2;

        xor             (xout[8], xin1[8], xin2[8]),
                        (xout[7], xin1[7], xin2[7]),
                        (xout[6], xin1[6], xin2[6]),
                        (xout[5], xin1[5], xin2[5]),
                        (xout[4], xin1[4], xin2[4]),
                        (xout[3], xin1[3], xin2[3]),
                        (xout[2], xin1[2], xin2[2]),
                        (xout[1], xin1[1], xin2[1]);
endmodule
//example 4.9




module xorx (xout, xin1, xin2);
parameter                       width = 4,
                        delay = 10;
output          [1:width]               xout;
input           [1:width]               xin1, xin2;

        assign #delay xout = xin1 ^ xin2;
endmodule
//example 4.10





module xorsAreUs (a1, a2);
output          [3:0]           a1, a2;
reg     [3:0]                    b1, c1, b2, c2;

        xorx            a(a1, b1, c1),
                        b(a2, b2, c2);
endmodule

module xorx (xout, xin1, xin2);
parameter                       width = 4,
                        delay = 10;
output          [1:width]               xout;
input           [1:width]               xin1, xin2;

        assign #delay xout = xin1 ^ xin2;
endmodule

module annotate;
        defparam
                xorsAreUs.b.delay = 5;
endmodule
//example 4.11




`define READ 0
`define WRITE 1

module sbus;
parameter
        Tclock = 20,
        Tprop = 5,
        Asize = 4,
        Dsize = 15,
        Msize = 31;

reg clock;

wire                    rw;
wire            [Asize:0]                       addr;
wire            [Dsize:0]                       data;

        master          #(Asize, Dsize, Tprop) 
                                m1 (rw, addr, data, clock);
        slave           #(Asize, Dsize, Msize, Tprop) 
                                s1 (rw, addr, data, clock);

initial
        begin
                clock = 0;
                forever
                        @(negedge clock) $display ("%d, data=%d, addr=%d at time %d",
                                                                        rw, data, 
addr, $time);
        end

always 
        #Tclock clock = !clock;
endmodule

module slave (rw, addressLines, dataLines, clock);
parameter
        Asize = 4,
        Dsize = 15,
        Msize = 31,
        Tprop = 5;
input           rw, clock;
input           [Asize:0]                       addressLines;
inout           [Dsize:0]                       dataLines;

reg             [Dsize:0]                       m[0:Msize];
reg             [Dsize:0]                       internalData;
reg             enable;

        busDriver                       #(Dsize)                         bSlave 
(dataLines, internalData, enable);

initial
        begin
                $readmemh ("memory.data", m);
                enable = 0;
        end

always           // bus slave end
        begin
                @(negedge clock);
                if (~rw) begin                          //read
                        #Tprop internalData = m[addressLines];
                        enable = 1;
                        @(negedge clock);
                        enable = 0;
                end
                else            //write
                        m[addressLines] = dataLines;
        end
endmodule

module master (rw, addressLines, dataLines, clock);
parameter
        Asize = 4,
        Dsize = 15,
        Tprop = 5;
input                                   clock;
output                                  rw;
output           [Asize:0]                      addressLines;
inout            [Dsize:0]                      dataLines;

reg                                     rw, enable;
reg              [Dsize:0]                      internalData;
reg              [Asize:0]                      addressLines;

        busDriver #(Dsize) bMaster (dataLines, internalData, enable);