📄 examplesa.txt
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counter
reg [31:0] acc; // 32 bit accumulator
reg [15:0] ir; // 16 bit instruction
register
always
begin
ir = m [pc];
case (ir [15:13])
3'b000 : pc = m [ir [12:0]];
3'b001 : pc = pc + m [ir
[12:0]];
3'b010 : acc = -m [ir [12:0]];
3'b011 : m [ir [12:0]] = acc;
3'b100,
3'b101 : acc = acc - m [ir
[12:0]];
3'b110 : if (acc < 0) pc = pc
+ 1;
3'b111 : acc = acc * m [ir
[12:0]]; //multiply
endcase
#1 pc = pc + 1;
end
endmodule
//example 2.8
module mark1Task;
reg [31:0] m [0:8191]; // 8192 x 32
bit memory
reg [12:0] pc; // 13 bit program
counter
reg [31:0] acc; // 32 bit accumulator
reg [15:0] ir; // 16 bit instruction
register
always
begin
ir = m [pc];
case (ir [15:13])
// other case expressions as before
3'b111 : multiply (acc, m [ir
[12:0]]);
endcase
#1 pc = pc + 1;
end
task multiply;
inout [31:0] a;
input [31:0 ] b;
reg [15:0] mcnd, mpy;
//multiplicand and multiplier
reg [31:0] prod;
//product
begin
mpy = b[15:0];
mcnd = a[15:0];
prod = 0;
repeat (16)
begin
if (mpy[0])
prod = prod + {mcnd, 16'h0000};
prod = prod >> 1;
mpy = mpy >> 1;
end
a = prod;
end
endtask
endmodule
//example 2.9
module mark1Fun;
reg [31:0] m [0:8191]; // 8192 x 32
bit memory
reg [12:0] pc; // 13 bit program
counter
reg [31:0] acc; // 32 bit accumulator
reg [15:0] ir; // 16 bit instruction
register
always
begin
ir = m [pc];
case (ir [15:13])
//case expressions, as before
3'b111: acc = multiply(acc, m [ir
[12:0]]);
endcase
#1 pc = pc + 1;
end
function [31:0] multiply;
input [31:0] a;
input [31:0] b;
reg [15:0] mcnd, mpy;
begin
mpy = b[15:0];
mcnd = a[15:0];
multiply = 0;
repeat (16)
begin
if (mpy[0])
multiply = multiply + {mcnd,
16'h0000};
multiply = multiply >> 1;
mpy = mpy >> 1;
end
end
endfunction
endmodule
//example 2.10
module mark1Mod;
reg [31:0] m [0:8191]; // 8192 x 32
bit memory
reg [12:0] pc; // 13 bit program
counter
reg [31:0] acc; // 32 bit accumulator
reg [15:0] ir; // 16 bit instruction
register
reg [31:0] mcnd;
reg go;
wire [31:0] prod;
wire done;
multiply mul (prod, acc, mcnd, go, done);
always
begin
go = 0;
ir = m [pc];
case (ir [15:13])
//other case expressions
3'b111: begin
mcnd = m [ir [12:0]];
go = 1;
wait (done);
acc = prod;
end
endcase
#1 pc = pc + 1;
end
endmodule
module multiply (prod, mpy, mcnd, go, done);
output [31:0] prod;
input [31:0 ] mpy, mcnd;
input go;
output done;
reg [31:0] prod;
reg [15:0] myMpy;
reg done;
always
begin
done = 0;
wait (go);
myMpy = mpy[15:0];
prod = 0;
repeat (16)
begin
if (myMpy[0])
prod = prod + {mcnd, 16'h0000};
prod = prod >> 1;
myMpy = myMpy >> 1;
end
done = 1;
wait (~go);
end
endmodule
//example 2.11
module dEdgeFF (q, clock, data);
output q;
reg q;
input clock, data;
initial
#10 q = 0;
always
@(negedge clock) #10 q = data;
endmodule
//examples 3.2 and 1.4
module topNE();
wire [15:0] number, numberOut;
numberGenNE ng(number);
fibNumberGenNE fng(number, numberOut);
endmodule
module numberGenNE(number);
output [15:0] number;
reg [15:0] number;
event ready;
initial
number = 0;
always
begin
#50 number = number + 1;
#50 -> ready; //generate
event signal
end
endmodule
module fibNumberGenNE(startingValue, fibNum);
input [15:0] startingValue;
output [15:0] fibNum;
reg [15:0] count, fibNum, oldNum, temp;
always
begin
@ng.ready //accept event
signal
count = startingValue;
oldNum = 1;
for (fibNum = 0; count != 0; count = count - 1)
begin
temp = fibNum;
fibNum = fibNum + oldNum;
oldNum = temp;
end
$display ("%d, fibNum=%d", $time, fibNum);
end
endmodule
//example 3.4
module consumer (dataIn, ready);
input [7:0] dataIn;
input ready;
reg [7:0] in;
always
begin
wait (ready)
in = dataIn;
//... consume dataIn
end
endmodule
//example 3.5
module consumer(dataIn, prodReady, consReady);
input [7:0] dataIn;
input prodReady;
output consReady;
reg consReady;
reg [7:0] dataInCopy;
always
begin
consReady = 1;
// indicate consumer ready
forever
begin
wait (prodReady)
dataInCopy = dataIn;
consReady = 0;
// indicate value consumed
//...munch on data
wait (!prodReady)
// complete handshake
consReady = 1;
end
end
endmodule
//example 3.6
module producer(dataOut, prodReady, consReady);
output [7:0] dataOut;
output prodReady;
input consReady;
reg prodReady;
reg [7:0] dataOut;
always
begin
prodReady = 0;
// indicate nothing to transfer
forever
begin
// ...produce data and put into "dataOut"
wait (consReady)
// wait for consumer ready
dataOut = $random;
prodReady = 1;
//indicate ready to transfer
wait (!consReady)
//finish handshake
prodReady = 0;
end
end
endmodule
//example 3.7
module ProducerConsumer;
wire [7:0] data;
wire pReady, cReady;
producer p (data, pReady, cReady);
consumer c (data, pReady, cReady);
endmodule
//example 3.8
module endlessLoop (inputA);
input inputA;
reg [15:0] count;
always
begin
count = 0;
while (inputA)
count = count + 1; //
wait for inputA to change to FALSE
$display ("This will never print if inputA is TRUE!");
end
endmodule
//example 3.9
`define READ 0
`define WRITE 1
module sbus;
parameter
tClock = 20,
tProp = 5;
reg clock;
reg [15:0] m[0:31]; //32 16-bit words
reg [15:0] data;
// registers names xLine model the bus lines using global registers
reg rwLine; //write = 1, read = 0
reg [4:0] addressLines;
reg [15:0] dataLines;
initial
begin
$readmemh ("memory.data", m);
clock = 0;
forever
@(negedge clock)
$display ("%d, data=%d, addr=%d at time %d", rwLine,
dataLines, addressLines, $time);
end
always
#tClock clock = !clock;
initial // bus master end
begin
wiggleBusLines ( `READ, 2, data);
wiggleBusLines ( `READ, 3, data);
data = 5;
wiggleBusLines ( `WRITE, 2, data);
data = 7;
wiggleBusLines ( `WRITE, 3, data);
wiggleBusLines ( `READ, 2, data);
wiggleBusLines ( `READ, 3, data);
$finish;
end
task wiggleBusLines;
input readWrite;
input [5:0] addr;
inout [15:0] data;
begin
#tProp
rwLine = readWrite;
if (readWrite) begin
// write value
addressLines = addr;
dataLines = data;
end
else begin //read value
addressLines = addr;
@ (negedge clock);
end
@(negedge clock);
if (~readWrite)
data = dataLines; //
value returned during read cycle
end
endtask
always // bus slave end
begin
@(negedge clock);
if (~rwLine) begin
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