examplesb.txt

熟悉verilog,帮助初学者尽快掌握verilog

          //reg [3:0] ran2;

                  initial begin
                          idx = 0;
                          rddata = 0;

          //              ave = 0 ;
          //              max = 0;
          //              count = 0;
                          ramp = 0;
                          flag = 1;
          //              z = 1;
                  
                          $readmemh("good.dat", disk);  
          //              ran =  $random(z);
                          
                  end 

                  //  set up the clock in rddata
          `protect
                  always begin
                          #(`P/8) rddata = 1;   // these will have to change later
                          #(`P/8) rddata = 0;   // to have some randomness
                          #(`P*0.7 + ramp); // delay between 280 and 
                                                       // 320 counts--2.8 and 3.2us
                          if (ramp == 40) 
                                  flag = -1;
                          if (ramp == 0) 
                                  flag = 1;
                          if (flag == 1)
                                  ramp = ramp + 1;
                          else 
                                  ramp = ramp - 1;
          //              ave = `P*0.7 +  ramp;
          //              $monitor($time,, ave);
                  end
          `endprotect
                  
                  // set up idx
          `protect
                  always begin
                          #(`P/8) idx = 1;
                          #(`P*8) idx = 0;
                          #(4087.875*`P) ;  // pulses per sector = 4096
                  end
          `endprotect
                  
                  // and put the data in rddata.
          `protect
                  always begin
                          for (sector=0; sector < 10; sector = sector + 1 ) 
                          begin
                                  for (byte=0; byte < 512; byte = byte + 1) 
                                  begin
                                          tmp = disk[sector*512 + byte];
                                          for (bit = 0; bit < 8; bit = bit + 1)
                                          begin
                                                  @(posedge rddata);
                                                  if ( tmp[bit] ) 
                                                  begin
                                                          #(0.5*(`P*0.7 + ramp+ `P/8));
                          // need to change this delay later to account for randomness
                                                          rddata = 1;
                                                          #(`P/8);
                                                          rddata = 0;     
                                                  end
                                          end
                                  end
                          end
                  end
          `endprotect
          endmodule
          //  disk module with correct data
          //  by Tom Martin, February 1995
          //  for 18-360.

          `define P 400           // period is 4 us...

          module disk(idx, rddata);
                  output idx, rddata;


          reg [7:0]       disk[0:5119];  // the 10 sectors of the disk
          reg idx, rddata;

          integer sector, byte, bit;
          reg [7:0] tmp;

                  initial begin
                          idx = 0;
                          rddata = 0;
                          $readmemh("bad.dat", disk);  
                  end 

                  //  set up the clock in rddata
          `protect
                  always begin
                          #(`P/8) rddata = 1;   // these will have to change later
                          #(`P/8) rddata = 0;   // to have some randomness
                          #(`P*0.75);
                  end
          `endprotect
                  
                  // set up idx
          `protect
                  always begin
                          #(`P/8) idx = 1;
                          #(`P*8) idx = 0;
                          #(4087.875*`P) ;
                  end
          `endprotect
                  
                  // and put the data in rddata.
          `protect
                  always begin
                          for (sector=0; sector < 10; sector = sector + 1 ) 
                          begin
                                  for (byte=0; byte < 512; byte = byte + 1) 
                                  begin
                                          tmp = disk[sector*512 + byte];
                                          for (bit = 0; bit < 8; bit = bit + 1)
                                          begin
                                                  @(posedge rddata);
                                                  if ( tmp[bit] ) 
                                                  begin
                                                          #(`P/2);
                                                          rddata = 1;
                                                          #(`P/8);
                                                          rddata = 0;     
                                                  end
                                          end
                                  end
                          end
                  end
          `endprotect
          endmodule
          //  memory.v  
          //  by Tom Martin for 18-360, February 1995.
          //  Models the memory bus controller and memory for
          //  use with the floppy disk controller (Project 1)


          //  bus clock is specified to be 8 MHz, or 125ns/cycle

          module memory(clock, hrq, hack, memw, d, a);
          parameter tProp = 1;

                  output clock, hack;
                  reg clock, hack;
                  input hrq, memw;

                  inout [7:0] d; 
                  inout [8:0] a;

                  reg debug;


          reg [7:0]       m[0:511];       //512 bytes of memory

                          initial begin
                                  clock = 0;
                                  hack = 0;
                                  debug = 0;
                                  //  set memory all to 0?
                          end
                          
                          //  the bus clock
                          always 
                                  #6.25 clock = ~clock;
          `protect
                          // the bus protocol
                          always begin
                                  @(posedge clock);
                                  if (hrq && ~hack)  begin
                                          #tProp;
                                          hack = 1;
                                  end
                                  else if (hrq && hack) begin 
                                          if (~memw) begin
                                                  @(negedge clock); 
                                                  m[a] = d;
                                                  @(posedge clock);
                                                  if (~memw) 
                                                    $display($time,,,"Memw high error");
                                          end  
                                  end
                                  else if (~hrq && hack ) begin
                                          #tProp;
                                          hack = 0;
                                  end
                          end
          `endprotect
                          //  debug stuff--print contents of memory.
                          //  to print contents of memory, just set debug = 1...

                          integer count;

                          always begin
                                  @(posedge debug);
                                  for (count = 0; count < 512; count = count + 1)
                                  begin
          //                              $write( "%0x ", m[count]);
                                          $write( "%c ", m[count]);
                                          if (( (count+1) % 25) == 0)
                                                  $display;
                                  end
                                  $display;
                          end
          endmodule
          //  disk module with correct data
          //  by Tom Martin, February 1995
          //  for 18-360.

          //  this particular module has a clock with jitter.

          `define P 400           // period is 4 us...

          module disk(idx, rddata);
                  output idx, rddata;


          reg [7:0]       disk[0:5119];  // the 10 sectors of the disk
          reg idx, rddata;

          integer sector, byte, bit, z;


          //  for testing random rddata clock
          integer ave, count, max;

          reg [7:0] tmp;
          reg [3:0] ran;
          reg [3:0] ran2;

                  initial begin
                          idx = 0;
                          rddata = 0;

                          ave = 0 ;
                          max = 0;
                          count = 0;
          //              $monitor($time,,rddata);

                          z = 1;
                  
                          $readmemh("good.dat", disk);  
                          ran =  $random(z);
                          
                  end 

                  //  set up the clock in rddata
          `protect
                  always begin
                          #(`P/8) rddata = 1;   // these will have to change later
                          #(`P/8) rddata = 0;   // to have some randomness
                          #(`P*0.7 + (40*ran)/15 ); // delay between 280 and 
                                                       // 320 counts--2.8 and 3.2us
                          ave = `P*0.7 + (40*ran)/15 + `P/4;
          //              $display(ave);
                          ran = $random;
                          count = count + 1;
          //              if (ave > max) 
          //                      max = ave;
          //              if (ave > 420) 
          //                      $stop;
                  end
          `endprotect
                  
                  // set up idx
          `protect
                  always begin
                          #(`P/8) idx = 1;
                          #(`P*8) idx = 0;
                          #(4087.875*`P) ;  // pulses per sector = 4096
                  end
          `endprotect
                  
                  // and put the data in rddata.
          `protect
                  always begin
                          for (sector=0; sector < 10; sector = sector + 1 ) 
                          begin
                                  for (byte=0; byte < 512; byte = byte + 1) 
                                  begin
                                          tmp = disk[sector*512 + byte];
                                          for (bit = 0; bit < 8; bit = bit + 1)
                                          begin
                                                  @(posedge rddata);
                                                  if ( tmp[bit] ) 
                                                  begin
                                                          ran2 = $random;
                                                  #(ave/2 - ave/40 + (ave/20)*ran2/15);
                                                          rddata = 1;
                                                          #(`P/8);
                                                          rddata = 0;     
                                                  end
                                          end
                                  end
                          end
                  end
          `endprotect
          endmodule
          //see separate files for good.dat and bad.dat