examplesb.txt

熟悉verilog,帮助初学者尽快掌握verilog

                `ValX: strengthVal = fillBits(eleStrength[evalElement]);
              endcase
          endfunction
           
          // Given an incomplete strength value, fill the missing strength bits.
          // The filling is only necessary when the value is unknown.
          function [15:0] fillBits;
          input [15:0] val;
            begin
              fillBits = val;
              if (log3(val) == `ValX)
                begin
                  casez (val)
            16'b1???????_????????: fillBits = fillBits | 16'b11111111_00000001;
            16'b01??????_????????: fillBits = fillBits | 16'b01111111_00000001;
            16'b001?????_????????: fillBits = fillBits | 16'b00111111_00000001;
            16'b0001????_????????: fillBits = fillBits | 16'b00011111_00000001;
            16'b00001???_????????: fillBits = fillBits | 16'b00001111_00000001;
            16'b000001??_????????: fillBits = fillBits | 16'b00000111_00000001;
            16'b0000001?_????????: fillBits = fillBits | 16'b00000011_00000001;
                  endcase
                  casez (val)
            16'b????????_1???????: fillBits = fillBits | 16'b00000001_11111111;
            16'b????????_01??????: fillBits = fillBits | 16'b00000001_01111111;
            16'b????????_001?????: fillBits = fillBits | 16'b00000001_00111111;
            16'b????????_0001????: fillBits = fillBits | 16'b00000001_00011111;
            16'b????????_00001???: fillBits = fillBits | 16'b00000001_00001111;
            16'b????????_000001??: fillBits = fillBits | 16'b00000001_00000111;
            16'b????????_0000001?: fillBits = fillBits | 16'b00000001_00000011;
                 endcase
               end
            end
          endfunction
           
          // Evaluate a 'Nand' gate primitive.
          task evalNand;
          input fanout; //first or second fanout indicator
            begin
              storeInVal(fanout);
              // calculate new output value
              in0 = log3(in0Val[evalElement]);
              in1 = log3(in1Val[evalElement]);
              out = ((in0 == `Val0) || (in1 == `Val0)) ?
                  strengthVal(`Val1) :
                  ((in0 == `ValX) || (in1 == `ValX)) ?
                      strengthVal(`ValX):
                      strengthVal(`Val0);
              // schedule if output value is different
              if (out != outVal[evalElement])
                  schedule(out);
            end
          endtask
           
          // Evaluate a D positive edge-triggered flip flop
          task evalDEdgeFF;
          input fanout; //first or second fanout indicator
              // check value change is on clock input
              if (fanout ? (fo1TermNum[eventElement] == 0) :
                           (fo0TermNum[eventElement] == 0))
                begin
                  // get old clock value
                  oldIn0 = log3(in0Val[evalElement]);
                  storeInVal(fanout);
                  in0 = log3(in0Val[evalElement]);
                  // test for positive edge on clock input
                  if ((oldIn0 == `Val0) && (in0 == `Val1))
                    begin
                      out = strengthVal(log3(in1Val[evalElement]));
                      if (out != outVal[evalElement])
                        schedule(out);
                    end
                end
              else
                  storeInVal(fanout); // store data input value
          endtask
           
          // Evaluate a wire with full strength values
          task evalWire;
          input fanout;
          reg [7:0] mask;
            begin
              storeInVal(fanout);
           
              in0 = in0Val[evalElement];
              in1 = in1Val[evalElement];
              mask = getMask(in0[15:8]) & getMask(in0[7:0]) &
                     getMask(in1[15:8]) & getMask(in1[7:0]);
              out = fillBits((in0 | in1) & {mask, mask});
           
              if (out != outVal[evalElement])
                  schedule(out);
           
              if (DebugFlags[2])
                  $display("in0 = %b_%b\nin1 = %b_%b\nmask= %b %b\nout = %b_%b",
                      in0[15:8],in0[7:0], in1[15:8],in1[7:0],
                      mask,mask, out[15:8],out[7:0]);
            end
          endtask
           
          // Given either a 0-strength or 1-strength half of a strength value
          // return a masking pattern for use in a wire evaluation.
          function [7:0] getMask;
          input [7:0] halfVal; //half a full strength value
              casez (halfVal)
                8'b???????1: getMask = 8'b11111111;
                8'b??????10: getMask = 8'b11111110;
                8'b?????100: getMask = 8'b11111100;
                8'b????1000: getMask = 8'b11111000;
                8'b???10000: getMask = 8'b11110000;
                8'b??100000: getMask = 8'b11100000;
                8'b?1000000: getMask = 8'b11000000;
                8'b10000000: getMask = 8'b10000000;
                8'b00000000: getMask = 8'b11111111;
              endcase
          endfunction
           
          // Schedule the evaluation element to change to a new value.
          // If the element is already scheduled then just insert the new value.
          task schedule;
          input [15:0] newVal; // new value to change to
            begin
              if (DebugFlags[0])
                  $display(
                      "Element %0d, type %0s, scheduled to change to %s(%b_%b)",
                      evalElement, typeString(eleType[evalElement]),
                      valString(newVal), newVal[15:8], newVal[7:0]);
              if (! schedPresent[evalElement])
                begin
                  schedList[evalElement] = nextList;
                  schedPresent[evalElement] = 1;
                  nextList = evalElement;
                end
              outVal[evalElement] = newVal;
            end
          endtask
          endmodule
          //example 8.1


          //  simulation interface module
          //  by Tom Martin, February, 1995 
          //  for 18-360 project 1.
          //  
          //  This module should be listed first on the command line, so that
          //  the timescale directive will apply to all other modules, i.e.,
          //  verilog simint.v blah1.v blah2.v blah3.v
          //  
          //  I think the simulator will die if the timescale directive is not
          //  in the first module, but is in later ones.

          `timescale      10 ns/1 ns
            
          module simint(go, count, done, err);
                  output go;
                  output [3:0] count;
                  reg go;
                  reg [3:0] count;
                  input done, err; 

                  initial begin
                          go = 0;
                          count = 0;
                  end

          endmodule
          Last modified:3/6/95, by Tom Martin

          The files in this directory are for the 18-360 Intro. to CAD project 1.

          Name            Description
          -------------------------------------------------------------------------
          memory.v        Verilog module for the 512 bytes of memory and the
                          memory bus controller.    Note that a useful feature
                          of memory.v is that the entire contents of the memory
                          can be displayed on the postive edge of 'debug'.  

          correct0.v      Verilog module for 10 sectors of a disk.  Uses the file
                          good.dat as input.  All 10 sectors of the disk are error
                          free.  

          error0.v        Verilog module for 10 sectors of a disk.  Uses the file
                          bad.dat as input.  Sectors 0, 1, 2 have errors in them;
                          sectors 3-9 are correct

          simint.v        Simulation interface module.  Used to start the simulation
                          and see when it is done.  This probably isn't
                          necessary--just have the top level of the design
                          connect to the go, sector count, done, and error
                          signals of Wait.  Contains the timescale directive
                          which sets the time units for the whole simulation.
                          simint.v should be the first module listed on the
                          command line in order to avoid compilation errors,
                          i.e.  verilog simint.v blah1.v blah2.v


          Comments
          ----------------------------------------------------------------------------

          3/3/95          Removed the timescale directives from memory.v,
                          correct0.v, and error0.v.  Simint.v now sets the 
                          time scale for the whole simulation (10ns/1ns).  
                          Modified the clock definition in correct0.v and error0.v
                          to account for the change in the time scale.

          3/6/95          Simint.v modified so that count is a 4 bit number
                          instead of a 3 bit number.  Thanks to Edith and the Chinman
                          for pointing out that you can't count to 10 with 3
                          bits...

          3/7/95          Memory.v modified so that the address bits could address
                          477 bytes of memory.  Variable a was changed from 8 bits
                          to 9 bits.

          3/10/95         Replaced the protected versions of correct0.v, error0.v,
                          and memory.v with their unprotected source, so that the
                          Cadence debugger can be used with the files.
          //  disk module with correct data
          //  by Tom Martin, February 1995
          //  for 18-360.

          `define P 400           // period is 4 us...

          module disk(idx, rddata);
                  output idx, rddata;


          reg [7:0]       disk[0:5119];  // the 10 sectors of the disk
          reg idx, rddata;

          integer sector, byte, bit;
          reg [7:0] tmp;

                  initial begin
                          idx = 0;
                          rddata = 0;
                          $readmemh("good.dat", disk);  
                  end 

                  //  set up the clock in rddata
          `protect
                  always begin
                          #(`P/8) rddata = 1;   // these will have to change later
                          #(`P/8) rddata = 0;   // to have some randomness
                          #(`P*0.75);
                  end
          `endprotect
                  
                  // set up idx
          `protect
                  always begin
                          #(`P/8) idx = 1;
                          #(`P*8) idx = 0;
                          #(4087.875*`P) ;
                  end
          `endprotect
                  
                  // and put the data in rddata.
          `protect
                  always begin
                          for (sector=0; sector < 10; sector = sector + 1 ) 
                          begin
                                  for (byte=0; byte < 512; byte = byte + 1) 
                                  begin
                                          tmp = disk[sector*512 + byte];
                                          for (bit = 0; bit < 8; bit = bit + 1)
                                          begin
                                                  @(posedge rddata);
                                                  if ( tmp[bit] ) 
                                                  begin
                                                          #(`P/2);
                                                          rddata = 1;
                                                          #(`P/8);
                                                          rddata = 0;     
                                                  end
                                          end
                                  end
                          end
                  end
          `endprotect
          endmodule
          //  disk module with correct data
          //  by Tom Martin, February 1995
          //  for 18-360.

          //  this particular module has a clock with ramping jitter

          `define P 400           // period is 4 us...

          module disk(idx, rddata);
                  output idx, rddata;


          reg [7:0]       disk[0:5119];  // the 10 sectors of the disk
          reg idx, rddata;

          integer sector, byte, bit, z;
          integer ramp, flag;

          //  for testing random rddata clock
          //  integer ave, count, max;

          reg [7:0] tmp;
          //reg [3:0] ran;