📄 bnf.txt
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/*
Copyright -c- 1996, Kluwer Academic Publishers. All Rights Reserved.
This electronic text file is distributed by Kluwer Academic Publishers with
*ABSOLUTELY NO SUPPORT* and *NO WARRANTY* from Kluwer
Academic Publishers.
Use or reproduction of the information provided in this electronic text file for
commercial gain is strictly prohibited. Explicit permission is given for the
reproduction and use of this information in an instructional setting provided
proper reference is given to the original source. Kluwer Academic Publishers
shall not be liable for damage in connection with, or arising out of, the furnis
hing,
performance or use of this information.
From the Authors:
This file contains support files for the floppy disk exercise in Chapter 9 of "T
he Verilog Hardware Description Language, Third Edition" by D. E. Thomas and
P. R. Moorby. Note that corrections may have been made to the examples in this
file and thus they may differ from the examples in the book. Later printings of
the
book will include these corrections. This file contains the good and bad data f
iles. You'll
need to save them to different files.
-always
DT, PM
*/
// simulation interface module
// by Tom Martin, February, 1995
// for 18-360 project 1.
//
// This module should be listed first on the command line, so that
// the timescale directive will apply to all other modules, i.e.,
// verilog simint.v blah1.v blah2.v blah3.v
//
// I think the simulator will die if the timescale directive is not
// in the first module, but is in later ones.
`timescale 10 ns/1 ns
module simint(go, count, done, err);
output go;
output [3:0] count;
reg go;
reg [3:0] count;
input done, err;
initial begin
go = 0;
count = 0;
end
endmodule
Last modified:3/6/95, by Tom Martin
The files in this directory are for the 18-360 Intro. to CAD project 1.
Name Description
-------------------------------------------------------------------------
memory.v Verilog module for the 512 bytes of memory and the
memory bus controller. Note that a useful feature
of memory.v is that the entire contents of the memory
can be displayed on the postive edge of 'debug'.
correct0.v Verilog module for 10 sectors of a disk. Uses the file
good.dat as input. All 10 sectors of the disk are error
free.
error0.v Verilog module for 10 sectors of a disk. Uses the file
bad.dat as input. Sectors 0, 1, 2 have errors in them;
sectors 3-9 are correct
simint.v Simulation interface module. Used to start the simulation
and see when it is done. This probably isn't
necessary--just have the top level of the design
connect to the go, sector count, done, and error
signals of Wait. Contains the timescale directive
which sets the time units for the whole simulation.
simint.v should be the first module listed on the
command line in order to avoid compilation errors,
i.e. verilog simint.v blah1.v blah2.v
Comments
----------------------------------------------------------------------------
3/3/95 Removed the timescale directives from memory.v,
correct0.v, and error0.v. Simint.v now sets the
time scale for the whole simulation (10ns/1ns).
Modified the clock definition in correct0.v and error0.v
to account for the change in the time scale.
3/6/95 Simint.v modified so that count is a 4 bit number
instead of a 3 bit number. Thanks to Edith and the Chinman
for pointing out that you can't count to 10 with 3
bits...
3/7/95 Memory.v modified so that the address bits could address
477 bytes of memory. Variable a was changed from 8 bits
to 9 bits.
3/10/95 Replaced the protected versions of correct0.v, error0.v,
and memory.v with their unprotected source, so that the
Cadence debugger can be used with the files.
// disk module with correct data
// by Tom Martin, February 1995
// for 18-360.
`define P 400 // period is 4 us...
module disk(idx, rddata);
output idx, rddata;
reg [7:0] disk[0:5119]; // the 10 sectors of the disk
reg idx, rddata;
integer sector, byte, bit;
reg [7:0] tmp;
initial begin
idx = 0;
rddata = 0;
$readmemh("good.dat", disk);
end
// set up the clock in rddata
`protect
always begin
#(`P/8) rddata = 1; // these will have to change later
#(`P/8) rddata = 0; // to have some randomness
#(`P*0.75);
end
`endprotect
// set up idx
`protect
always begin
#(`P/8) idx = 1;
#(`P*8) idx = 0;
#(4087.875*`P) ;
end
`endprotect
// and put the data in rddata.
`protect
always begin
for (sector=0; sector < 10; sector = sector + 1 )
begin
for (byte=0; byte < 512; byte = byte + 1)
begin
tmp = disk[sector*512 + byte];
for (bit = 0; bit < 8; bit = bit + 1)
begin
@(posedge rddata);
if ( tmp[bit] )
begin
#(`P/2);
rddata = 1;
#(`P/8);
rddata = 0;
end
end
end
end
end
`endprotect
endmodule
// disk module with correct data
// by Tom Martin, February 1995
// for 18-360.
// this particular module has a clock with ramping jitter
`define P 400 // period is 4 us...
module disk(idx, rddata);
output idx, rddata;
reg [7:0] disk[0:5119]; // the 10 sectors of the disk
reg idx, rddata;
integer sector, byte, bit, z;
integer ramp, flag;
// for testing random rddata clock
// integer ave, count, max;
reg [7:0] tmp;
//reg [3:0] ran;
//reg [3:0] ran2;
initial begin
idx = 0;
rddata = 0;
// ave = 0 ;
// max = 0;
// count = 0;
ramp = 0;
flag = 1;
// z = 1;
$readmemh("good.dat", disk);
// ran = $random(z);
end
// set up the clock in rddata
`protect
always begin
#(`P/8) rddata = 1; // these will have to change later
#(`P/8) rddata = 0; // to have some randomness
#(`P*0.7 + ramp); // delay between 280 and
// 320 counts--2.8 and 3.2us
if (ramp == 40)
flag = -1;
if (ramp == 0)
flag = 1;
if (flag == 1)
ramp = ramp + 1;
else
ramp = ramp - 1;
// ave = `P*0.7 + ramp;
// $monitor($time,, ave);
end
`endprotect
// set up idx
`protect
always begin
#(`P/8) idx = 1;
#(`P*8) idx = 0;
#(4087.875*`P) ; // pulses per sector = 4096
end
`endprotect
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