compilefsm.v

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//有限状态机

//Example 1
//采用Gray码
module fsm1 (Clock, Reset, A, F, G);
	input Clock, Reset, A;
	output F, G;
	reg F, G;
	reg [1:0] state;
	
	parameter Idle = 2'b00, Start = 2'b01,
		    Stop = 2'b10, Clear = 2'b11;
	
	always @ (posedge Clock)
		if (!Reset)
			begin
				state <= Idle; F <= 0; G <= 0;
			end
		else
		   case (state)
		   	Idle:	begin
		   		   if (A) state <= Start;
		   		   G <= 0;
		   		end
		   	Start:if (!A) state <=Stop;
		   	Stop:	begin
		   		   if (A) state <= Clear;
		   		   F <= 1;
		   		end
		   	Clear:begin
		   		if (!A) state <= Idle;
		   			F <= 0; G <= 1;
		   		end
		   endcase
	
endmodule



//Example 2
/*采用独热编码(one-hot-coding)    适用于FPGA实现的有限状态机,多用了两个触发器,
但省下了许多组合电路,而总的单元数却增加不多，使电路的速度和可靠性有显著提高。
会出现多余状态，需增加default分支项。  */
module fsm2 (Clock, Reset, A, F, G);
	input Clock, Reset, A;
	output F, G;
	reg F, G;
	reg [3:0] state;
	
	parameter Idle = 4'b1000,
		    Start = 4'b0100,
		    Stop = 4'b0010,
		    Clear = 4'b0001;
	
	always @ (posedge Clock)
		if (!Reset)
			begin
				state <= Idle; F <= 0; G <= 0;
			end
		else
		   case (state)
		   	Idle:	begin
		   		   if (A) state <= Start;
		   		   G <= 0;
		   		end
		   	Start:if (!A) state <=Stop;
		   	Stop:	begin
		   		   if (A) state <= Clear;
		   		   F <= 1;
		   		end
		   	Clear:begin
		   		if (!A) state <= Idle;
		   			F <= 0; G <= 1;
		   		end
		   	default:
		   		state <= Idle;
		   endcase
	
endmodule




//Example 3
/*    用always语句和连续赋值语句把状态机的触发器部分和组合逻辑部分分成两个部分
      来描述
*/
module fsm3 (Clock, Reset, A, F, G);
	input Clock, Reset, A;
	output F, G;
	reg [1:0] state;
	wire [1:0] Nextstate;
	
	parameter Idle = 2'b00, Start = 2'b01,
		    Stop = 2'b10, Clear = 2'b11;
	
	always @ (posedge Clock)
		if (!Reset)
			begin
				state <= Idle;
			end
		else
			state <= Nextstate;
	
	assign Nextstate = (state == Idle) ? (A ? Start : Idle) :
				 (state == Start) ? (!A ? Stop : Start) :
				 (state == Stop) ? (A ? Clear : Stop) :
				 (state == Clear) ? (!A ? Idle : Clear) : Idle;
	assign F = (state == Clear);
	assign G = (state == Idle);
		
endmodule



//Example 4
/*    分别用沿触发的always语句和电平敏感的always语句把状态机的触发器部分和组合
      逻辑部分分成两个部分来描述
*/
module fsm4 (Clock, Reset, A, F, G);
	input Clock, Reset, A;
	output F, G;
	reg F, G;
	reg [1:0] state, Nextstate;
	
	parameter Idle = 2'b00, Start = 2'b01,
		    Stop = 2'b10, Clear = 2'b11;
	
	always @ (posedge Clock)
		if (!Reset)
			begin
				state <= Idle;
			end
		else
			state <= Nextstate;
	
	always @ (state or A)
		begin
	   		F = 0;
	   		G = 0;
			if (state == Idle)
				begin
					if (A)
						Nextstate = Start;
					else
						Nextstate = Idle;
					G = 1;
				end
			else
				if (state == Start)
					if (A)
						Nextstate = Stop;
					else
						Nextstate = Start;
				else
					if (state == Stop)
						if (A)
							Nextstate = Clear;
						else
							Nextstate = Stop;
					else
						if (state == Clear)
							begin
								if (!A)
									Nextstate = Idle;
								else
									Nextstate = Clear;
								F = 1;
							end
						else
							Nextstate = Idle;
		end
endmodule