compile examples.v

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//可综合风格的Verilog HDL模块实例

//*****************************************************************************
//*   组合逻辑电路设计实例										*
//*   Example 1~10										*
//*****************************************************************************


//Example 1: 8位加法器（用简单的算法描述）

module adder_8 (cout, sum, a, b, cin);
	output cout;
	output [7:0] sum;
	input cin;
	input [7:0] a, b;

	assign {cout, sum} = a + b + cin;

endmodule



//Example 2: 指令译码电路（用电平敏感的always块来设计组合逻辑）

`define plus	3'b0
`define minus	3'b1
`define band	3'b2
`define bor 	3'b3
`define unegate	3'b4
module alu (out, opcode, a, b);
	output [7:0] out;
	input [2:0] opcode;
	input [7:0] a, b;
	reg [7:0] out;

	always @ (opcode or a or b)
		begin
			case (opcode)
				`plus :	out = a + b;
				`minus:	out = a - b;
				`band :	out = a & b;
				`bor  :	out = a | b;
				`unegate:	out = ~a;
				default:	out = 8'hx;
			endcase
		end

endmodule



//Example 3: 利用task和电平敏感的always块设计后重组信号的组合逻辑

module sort4 (ra, rb, rc, rd, a, b, c, d);
	parameter t = 3;
	output [t:0] ra, rb, rc, rd;
	input [t:0] a, b, c, d;
	reg [t:0] ra, rb, rc, rd;

	always @ (a or b or c or d)
	//用电平敏感的always块描述组合逻辑
		begin
			reg [t:0] va, vb, vc, vd;
			{va, vb, vc, vd} = {a, b, c, d};
			sort2(va, vc);
			sort2(vb, vd);
			sort2(va, vb);
			sort2(vc, vd);
			sort2(vb, vc);
			{ra, rb, rc, rd} = {va, vb, vc, vd}；
		end
	
	task sort2;
		inout [t:0] x, y;
		reg [t:0] tmp;
		if (x > y)
		   begin
		   	tmp = x;
		   	x = y;
		   	y = tmp;
		   end
	endtask

endmodule



//Example 4: 比较器的设计实例（利用赋值语句设计组合逻辑）

module compare (equal, a, b);
	parameter size = 1;
	output equal;
	input [size-1:0] a, b;
	
	assign equal = (a == b) ? 1 : 0;
	
endmodule




//Example 5: 3-8译码器设计实例（利用赋值语句设计组合逻辑）

module decoder (out, in);
	output [7:0] out;
	input [2:0] in;
	
	assign out = 1'b1 << in;
	/*****  把最低位的1左移in（根据从in口输入的值）位，并赋予out  *****/
	
endmodule



//Example 6: 8-3编码器的设计实例
//方案一：
module encoder1 (none_on, out, in);
	output none_on;
	output [2:0] out;
	input [7:0] in;
	reg [2:0] out;
	reg none_on;
	
	always @ (in)
	   begin: local
	   	integer i;
	   	out = 0;
	   	none_on = 1;
	   	/*  returns the value of the highest bit number turned on  */
	   	for (i = 0; i < 8; i = i + 1)
	   	   begin
	   	   	if (in[i])
	   	   	   begin
	   	   	   	out = i;
	   	   	   	none_on = 0;
	   	   	   end
	   	   end
	   end
	
endmodule

//方案二：
module encoder2 (none_on, out2, out1, out0, h, g, f, e, d, c, b, a);
	input h, g, f, e, d, c, b, a;
	output none_on, out2, out1, out0;
	wire [3:0] outvec;
	
	assign outvec = h ? 4'b0111 : g ? 4'b0110 : f ? 4'b0101 :
		e ? 4'b0100 : d ? 4'b0011 : c ? 4'b0010 : b ? 4'b0001 :
		a ? 4'b0000 : 4'b1000;
	
	assign none_on = outvec[3];
	assign out2 = outvec[2];
	assign out1 = outvec[1];
	assign out0 = outvec[0];

endmodule

//方案三：
module encoder3 (none_on, out2, out1, out0, h, g, f, e, d, c, b, a);
	input h, g, f, e, d, c, b, a;
	output out2, out1, out0;
	output none_on;
	reg [3:0] outvec;
	
	assign {none_on, out2, out1, out0} = outvec;
	
	always @ (a or b or c or d or e or f or g or h)
	   begin
	   	if (h)		outvec = 4'b0111;
	   	else if (g)		outvec = 4'b0110;
	   	else if (f)		outvec = 4'b0101;
	   	else if (e)		outvec = 4'b0100;
	   	else if (d)		outvec = 4'b0011;
	   	else if (c)		outvec = 4'b0010;
	   	else if (b)		outvec = 4'b0001;
	   	else if (a)		outvec = 4'b0000;
	   	else			outvec = 4'b1000;
	   end

endmodule



//Example 7: 多路器的设计实例
/*** 使用连续赋值、case语句和if-else语句可以生成多路器电路。如果条件语句（case或
**** if-else）中分支条件是互斥的话，综合器能自动地生成并行的多路器。   */

//方案一：
module mux1 (out, a, b, sel);
	output out;
	input a, b, sel;
	
	assign out = sel ? a : b;
	
endmodule

//方案二：
module mux2 (out, a, b, sel);
	output out;
	input a, b, sel;
	reg out;
	
	//用电平触发的always块来设计多路器的组合逻辑
	always @ (a or b or sel)
	   begin
	   	/*   检查输入信号sel的值，如为1，输出out为a；如为0，输出out为b   */
	   	case (sel)
	   		1'b1:		out = a;
	   		1'b0:		out = b;
	   		default:	out = 'bx;
	   	endcase
	   end

endmodule

//方案三：
module mux3 (out, a, b, sel);
	output out;
	input a, b, sel;
	reg out;
	
	always @ (a or b or sel)
	   begin
	   	if (sel)
	   		out = a;
	   	else
	   		out = b;
	   end

endmodule



//Example 8: 奇偶校验位生成器设计实例

module parity (even_numbits, odd_numbits, input_bus);
	output even_numbits, odd_numbits;
	input [7:0] input_bus;
	
	assign odd_numbits = ^ input_bus;
	assign even_numbits = ~ odd_numbits;
	
endmodule



//Example 9: 三态输出驱动器的设计实例（用连续赋值语句建立三态门模型）
//方案一：
module trist1 (out, in, enable);
	output out;
	input in, enable;
	
	assign out = enable ? in : 'bz;
	
endmodule

//方案二：
module trist2 (out, in, enable);
	output out;
	input in, enable;
	
	bufif1 mybuf1 (out, in, enable);
	//bufif1是一个Verilog门级原语(primitive)

endmodule


//Example 10: 三态双向驱动器设计实例

module bidir (tri_inout, out, in, en, b);
	inout tri_inout;
	output out;
	input in, en, b;
	
	assign tri_inout = en ? in : 'bz;
	assign out = tri_inout ^ b;
	
endmodule



//*****************************************************************************
//*   时序逻辑电路设计实例										*
//*   Example 1~7											*
//*****************************************************************************


//Example 1: 触发器设计实例

module dff (q, data, clk);
	output q;
	input data, clk;
	reg q;

	always @ (posedge clk)
	   begin
	   	q = data;
	   end

endmodule



//Example 2: 电平敏感型锁存器设计实例之一

module latch1 (q, data, clk);
	output q;
	input data, clk;
	reg q;

	assign q = clk ? data : q;
	
endmodule


//Example 3: 带置位和复位端的电平敏感型锁存器设计实例之二

module latch2 (q, data, clk, set, reset);
	output q;
	input data, clk, set, reset;
	reg q;

	assign q = clk ? data : q;
	
endmodule


//Example 4: 电平敏感型锁存器设计实例之三

module latch3 (q, data, clk);
	output q;
	input data, clk;
	reg q;

	always @ (clk or data)
	   begin
	   	if (clk)
	   		q = data;
	   end
	
endmodule




//Example 5: 移位寄存器设计实例

module shifter (din, clk, clr, dout);
	input din, clk, clr;
	output [7:0] dout;
	reg [7:0] dout;

	always @ (posedge clk)
	   begin
	   	if (clr)		//清零
	   		dout = 8'b0;
	   	else
	   	   begin
	   	   	dout = dout << 1;		//左移一位
	   	   	dout[0] = din;		//把输入信号放入寄存器的最低位
	   	   end
	   end
	
endmodule




//Example 6: 8位计数器设计实例之一

module counter1 (out, cout, data, load, cin, clk);
	output [7:0] out;
	output cout;
	input [7:0] data;
	input load, cin, clk;
	reg [7:0] out;

	always @ (posedge clk)
	   begin
	   	if (load)
	   		out = data;
	   	else
	   		out = out + cin;
	   end
	assign cout = & out & cin;
	
endmodule




//Example 7: 8位计数器设计实例之二

module counter2 (out, cout, data, load, cin, clk);
	output [7:0] out;
	output cout;
	input [7:0] data;
	input load, cin, clk;
	reg [7:0] out;
	reg cout;
	reg [7:0] preout;		//创建8位寄存器

	always @ (posedge clk)
	   begin
	   	out = preout;
	   end
	/*****  计算计数器和进位的下一个状态。注意：为提高性能不希望加载影响进位   *****/
	always @ (out or data or load or cin)
	   begin
	   	{cout, preout} = out + cin;
	   	if (load)
	   		preout = data;
	   end
	
endmodule