examples of verilog.v

熟悉verilog,帮助初学者尽快掌握verilog

// 模块的基本语法框架
//*******************   start   ***********************
module module_name (port_list);
  Declarations:
	reg,	wire,	parameter,
	input, output, inout,
	function, task, ...
	
  Statements:
	Initial statement
	Always statement
	Module instantiation
	Gate	instantiation
	UPD instantiation
	Continuous	assignment
endmodule
//*******************    end    ***********************


//*****************************************************************************
//* 通过 ModelSim EE/Plus 5.2c 编译的两个例子。                               *
//* The examples listed next is complied correctly by ModelSim EE/Plus 5.2c.  *
//*****************************************************************************

module HalfAdder (A, B,	Sum, Carry);
	input	A, B;
	output Sum,	Carry;
	
	assign #2 Sum = A ^ B;
	assign #5 Carry = A & B;
endmodule



module FA_Mix ( A, B, Cin, Sum, Cout );
	input A, B, Cin;
	output Sum, Cout;
	reg Cout;
	reg T1, T2, T3;
	wire S1;
	
	xor X1 (S1, A, B);    //门实例语句。
	
	always @ ( A or B or Cin ) 
		begin
			T1 = A & Cin;
			T2 = B & Cin;
			T3 = A & B;
			Cout = ( T1 | T2 ) | T3;
		end
	
	assign Sum = S1 ^ Cin;
endmodule
//*****************************************************************************




//*****************************************************************************
//* 通过 ModelSim EE/Plus 5.2c 仿真的例子。                                   *
//* The examples listed next is simulated correctly by ModelSim EE/Plus 5.2c. *
//*****************************************************************************

//  Example 1: wave test
// ++++++++++++++++++++++++++++++++++++++++++++++
`timescale 1ns/1ns
module Test ( Pop, Pid);
	output Pop, Pid;
	reg Pop, Pid;
	
	initial
	   begin
	        Pop = 0;
	        Pid = 0;
	        Pop = #5 1;
	        Pid = #3 1;
	        Pop = #6 0;
	        Pid = #2 0;
	    end
endmodule
// ----------------------------------------------


//   Example 2: Decoder2x4
// ++++++++++++++++++++++++++++++++++++++++++++++
`timescale 1ns/1ns
module Top;
	reg PA, PB, PEN;
	wire [3:0] PZ;
	
	//The module is need testing.
	Decoder2x4 Decoder1 (PA, PB, PEN, PZ);
	
	initial
		begin
			PEN = 0;
			PA = 0;
			PB = 0;
			PEN = #5 1;
			PA = #10 1;
			PB = #5 1;
			PA = #5 0;
			PB = #10 0;
		end
endmodule

module Decoder2x4 (A, B, EN, Z);
	input A, B, EN;
	output [3:0] Z;
	wire Abar, Bbar;
	
	assign #1 Abar = ~ A;
	assign #1 Bbar = ~ B;
	assign #2 Z[0] = ~ (Abar & Bbar & EN);
	assign #2 Z[1] = ~ (Abar & B & EN);
	assign #2 Z[2] = ~ (A & Bbar & EN);
	assign #2 Z[3] = ~ (A & B & EN);
endmodule
// ----------------------------------------------



//  Example 3: FA_Seq
// ++++++++++++++++++++++++++++++++++++++++++++++
`timescale 1ns/1ns
module Top;
	reg PA, PB, PCi;
	wire PCo, PSum;
	
	//The model being tested
	FA_Seq F1 (PA, PB, PCi, PSum, PCo);
	initial
		begin: ONLY_ONCE
			reg [3:0] Pal;
			
			for (Pal = 0; Pal < 8; Pal = Pal + 1)
				begin
				  { PA, PB, PCi} = Pal;
				  #5 $display ( "PA, PB, PCi = %b  %b  %b", PA, PB, PCi,
				  		" : : : PCo, PSum = %b  %b" , PCo, PSum );
				end
		end
endmodule

module FA_Seq (A, B, Cin, Sum, Cout);
	input A, B, Cin;
	output Sum, Cout;
	reg Sum, Cout;
	reg T1, T2, T3;
	always
	  @ ( A or B or Cin ) begin
		Sum = ( A ^ B ) ^ Cin;
		T1 = A & Cin;
		T2 = B & Cin;
		T3 = A & B;
		Cout = ( T1 | T2 ) | T3;
	  end
endmodule
// ----------------------------------------------



//  Example 4: Four-Bit-Castic-Adder
// ++++++++++++++++++++++++++++++++++++++++++++++
//Test the Four-Bit-Castic-Adder
`timescale 1ns/1ns
module Top;
	reg [3:0] PA, PB;
	reg PCin;
	wire PCout;
	wire [3:0] PSum;
	
	//The model being tested
	FourBitFA F4Aone (PA, PB, PCin, PSum, PCout);
	initial
		begin: ONLY_ONCE
			reg [4:0] Pal, Pbl;
			
			for (Pal = 0; Pal < 16; Pal = Pal + 1)
				for (Pbl = 0; Pbl < 16; Pbl = Pbl + 1)
					begin
					  PA = Pal;
					  PB = Pbl;
					  PCin = 0;
					  #5 $display ( "PA,  PB,  PCin  =  %b  %b  %b", PA, PB, PCin,
					  		"  : : :  PCout,  PSum  =  %b  %b" , PCout, PSum );
					  PCin = 1;
					  #5 $display ( "PA,  PB,  PCin  =  %b  %b  %b", PA, PB, PCin,
					  		"  : : :  PCout,  PSum  =  %b  %b" , PCout, PSum );
					  
					end
		end
endmodule

module FourBitFA ( FA, FB, FCin, FSum, FCout );
	parameter SIZE = 4;
	input [SIZE:1] FA, FB;
	output [SIZE:1] FSum;
	input FCin;
	output FCout;
	wire [SIZE-1:1] FTemp;
	
	FA_Str
		FA1( .A( FA[1] ), .B( FB[1] ), .Cin( FCin ),
			.Sum( FSum[1] ), .Cout( FTemp[1] ) ),
		FA2( .A( FA[2] ), .B( FB[2] ), .Cin( FTemp[1] ),
			.Sum( FSum[2] ), .Cout( FTemp[2] ) ),
		FA3( .A( FA[3] ), .B( FB[3] ), .Cin( FTemp[2] ),
			.Sum( FSum[3] ), .Cout( FTemp[3] ) ),
		FA4( .A( FA[4] ), .B( FB[4] ), .Cin( FTemp[3] ),
			.Sum( FSum[4] ), .Cout( FCout ) );
endmodule

module FA_Str ( A, B, Cin, Sum, Cout );
	input A, B, Cin;
	output Sum, Cout;
	wire S1, T1, T2, T3;
	
	xor
		X1 (S1, A, B),
		X2 (Sum, S1, Cin);
	and
		A1 (T3, A, B),
		A2 (T2, B, Cin),
		A3 (T1, A, Cin);
	or
		O1 (Cout, T1, T2, T3);
endmodule
// ----------------------------------------------



//  Example 5: RS_FF
// ++++++++++++++++++++++++++++++++++++++++++++++
`timescale 10ns/1ns
module RS_FF (Q, Qbar, R, S);
	output Q, Qbar;
	input R, S;
	
	nand #1 (Q, R, Qbar);
	nand #1 (Qbar, S, Q);
endmodule

module Test;
	reg TS, TR;
	wire TQ, TQb;
	
	RS_FF NSTA ( .Q(TQ), .S(TS), .R(TR), .Qbar(TQb));
	
	initial
		begin
			TR = 0;
			TS = 0;
			#5 TS = 1;
			#5 TS = 0;
			TR = 1;
			#5 TS = 1;
			TR = 0;
			#5 TS = 0;
			#5 TR = 1;
		end
	initial
		$monitor ( "At time %t ,  " , $time,
			"  TR = %b,   TS = %b,   TQ = %b,   TQb = %b", TR, TS, TQ, TQb);
endmodule
// ----------------------------------------------



//  Example 6: 
// ++++++++++++++++++++++++++++++++++++++++++++++

// ----------------------------------------------




//  Example 7: 
// ++++++++++++++++++++++++++++++++++++++++++++++

// ----------------------------------------------




//  Example 8: 
// ++++++++++++++++++++++++++++++++++++++++++++++

// ----------------------------------------------

//*****************************************************************************