zhuangtai.map.qmsg

状态机的典型饮用

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 26 20:42:14 2007 " "Info: Processing started: Fri Oct 26 20:42:14 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off zhuangtai -c zhuangtai " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off zhuangtai -c zhuangtai" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../shixu/zhuangtai.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../shixu/zhuangtai.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 zhuangtai-first " "Info: Found design unit 1: zhuangtai-first" {  } { { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 zhuangtai " "Info: Found entity 1: zhuangtai" {  } { { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "zhuangtai " "Info: Elaborating entity \"zhuangtai\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "rst zhuangtai.vhd(15) " "Warning (10492): VHDL Process Statement warning at zhuangtai.vhd(15): signal \"rst\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 15 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "next_state zhuangtai.vhd(22) " "Warning (10631): VHDL Process Statement warning at zhuangtai.vhd(22): inferring latch(es) for signal or variable \"next_state\", which holds its previous value in one or more paths through the process" {  } { { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 22 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "next_state\[0\] zhuangtai.vhd(22) " "Info (10041): Verilog HDL or VHDL info at zhuangtai.vhd(22): inferred latch for \"next_state\[0\]\"" {  } { { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 22 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "next_state\[1\] zhuangtai.vhd(22) " "Info (10041): Verilog HDL or VHDL info at zhuangtai.vhd(22): inferred latch for \"next_state\[1\]\"" {  } { { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 22 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "next_state\[2\] zhuangtai.vhd(22) " "Info (10041): Verilog HDL or VHDL info at zhuangtai.vhd(22): inferred latch for \"next_state\[2\]\"" {  } { { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 22 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "y\[3\]~reg0 data_in GND " "Warning: Reduced register \"y\[3\]~reg0\" with stuck data_in port to stuck value GND" {  } { { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 15 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "y\[3\] GND " "Warning: Pin \"y\[3\]\" stuck at GND" {  } { { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 15 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0 0 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0}  } {  } 0 0 "Promoted pin-driven signal(s) to global signal" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "21 " "Info: Implemented 21 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "4 " "Info: Implemented 4 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_MCELLS" "12 " "Info: Implemented 12 macrocells" {  } {  } 0 0 "Implemented %1!d! macrocells" 0 0} { "Info" "ISCL_SCL_TM_SEXPS" "1 " "Info: Implemented 1 shareable expanders" {  } {  } 0 0 "Implemented %1!d! shareable expanders" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "139 " "Info: Allocated 139 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 26 20:42:16 2007 " "Info: Processing ended: Fri Oct 26 20:42:16 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}