📄 zhuangtai.tan.qmsg
字号:
{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "next_state\[1\]~26 " "Warning: Node \"next_state\[1\]~26\"" { } { { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 22 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0} } { { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 22 -1 0 } } } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "next_state\[2\]~33 " "Warning: Node \"next_state\[2\]~33\"" { } { { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 22 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0} } { { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 22 -1 0 } } } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "next_state\[0\]~40 " "Warning: Node \"next_state\[0\]~40\"" { } { { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 22 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0} } { { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 22 -1 0 } } } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 5 -1 0 } } { "d:/program files/altera/7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register current_state\[0\] register current_state\[0\] 32.26 MHz 31.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 32.26 MHz between source register \"current_state\[0\]\" and destination register \"current_state\[0\]\" (period= 31.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "26.000 ns + Longest register register " "Info: + Longest register to register delay is 26.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns current_state\[0\] 1 REG LC12 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC12; Fanout = 12; REG Node = 'current_state\[0\]'" { } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { current_state[0] } "NODE_NAME" } } { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns Mux4~141 2 COMB LC10 9 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC10; Fanout = 9; COMB Node = 'Mux4~141'" { } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "9.000 ns" { current_state[0] Mux4~141 } "NODE_NAME" } } { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 24 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(9.000 ns) 18.000 ns next_state\[0\]~40 3 COMB LOOP LC11 3 " "Info: 3: + IC(0.000 ns) + CELL(9.000 ns) = 18.000 ns; Loc. = LC11; Fanout = 3; COMB LOOP Node = 'next_state\[0\]~40'" { { "Info" "ITDB_PART_OF_SCC" "next_state\[0\]~40 LC11 " "Info: Loc. = LC11; Node \"next_state\[0\]~40\"" { } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { next_state[0]~40 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { next_state[0]~40 } "NODE_NAME" } } { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 22 -1 0 } } { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "9.000 ns" { Mux4~141 next_state[0]~40 } "NODE_NAME" } } { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 26.000 ns current_state\[0\] 4 REG LC12 12 " "Info: 4: + IC(2.000 ns) + CELL(6.000 ns) = 26.000 ns; Loc. = LC12; Fanout = 12; REG Node = 'current_state\[0\]'" { } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { next_state[0]~40 current_state[0] } "NODE_NAME" } } { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "22.000 ns ( 84.62 % ) " "Info: Total cell delay = 22.000 ns ( 84.62 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 15.38 % ) " "Info: Total interconnect delay = 4.000 ns ( 15.38 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "26.000 ns" { current_state[0] Mux4~141 next_state[0]~40 current_state[0] } "NODE_NAME" } } { "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "26.000 ns" { current_state[0] Mux4~141 next_state[0]~40 current_state[0] } { 0.000ns 2.000ns 0.000ns 2.000ns } { 0.000ns 7.000ns 9.000ns 6.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 6 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clk'" { } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns current_state\[0\] 2 REG LC12 12 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC12; Fanout = 12; REG Node = 'current_state\[0\]'" { } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { clk current_state[0] } "NODE_NAME" } } { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk current_state[0] } "NODE_NAME" } } { "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out current_state[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 6 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clk'" { } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns current_state\[0\] 2 REG LC12 12 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC12; Fanout = 12; REG Node = 'current_state\[0\]'" { } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { clk current_state[0] } "NODE_NAME" } } { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk current_state[0] } "NODE_NAME" } } { "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out current_state[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk current_state[0] } "NODE_NAME" } } { "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out current_state[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } } { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk current_state[0] } "NODE_NAME" } } { "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out current_state[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 15 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" { } { { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 15 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "26.000 ns" { current_state[0] Mux4~141 next_state[0]~40 current_state[0] } "NODE_NAME" } } { "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "26.000 ns" { current_state[0] Mux4~141 next_state[0]~40 current_state[0] } { 0.000ns 2.000ns 0.000ns 2.000ns } { 0.000ns 7.000ns 9.000ns 6.000ns } "" } } { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk current_state[0] } "NODE_NAME" } } { "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out current_state[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } } { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk current_state[0] } "NODE_NAME" } } { "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out current_state[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "current_state\[0\] d\[0\] clk 29.000 ns register " "Info: tsu for register \"current_state\[0\]\" (data pin = \"d\[0\]\", clock pin = \"clk\") is 29.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "28.000 ns + Longest pin register " "Info: + Longest pin to register delay is 28.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns d\[0\] 1 PIN PIN_4 3 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_4; Fanout = 3; PIN Node = 'd\[0\]'" { } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { d[0] } "NODE_NAME" } } { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 11.000 ns Mux4~141 2 COMB LC10 9 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC10; Fanout = 9; COMB Node = 'Mux4~141'" { } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "9.000 ns" { d[0] Mux4~141 } "NODE_NAME" } } { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 24 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(9.000 ns) 20.000 ns next_state\[0\]~40 3 COMB LOOP LC11 3 " "Info: 3: + IC(0.000 ns) + CELL(9.000 ns) = 20.000 ns; Loc. = LC11; Fanout = 3; COMB LOOP Node = 'next_state\[0\]~40'" { { "Info" "ITDB_PART_OF_SCC" "next_state\[0\]~40 LC11 " "Info: Loc. = LC11; Node \"next_state\[0\]~40\"" { } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { next_state[0]~40 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { next_state[0]~40 } "NODE_NAME" } } { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 22 -1 0 } } { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "9.000 ns" { Mux4~141 next_state[0]~40 } "NODE_NAME" } } { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 28.000 ns current_state\[0\] 4 REG LC12 12 " "Info: 4: + IC(2.000 ns) + CELL(6.000 ns) = 28.000 ns; Loc. = LC12; Fanout = 12; REG Node = 'current_state\[0\]'" { } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { next_state[0]~40 current_state[0] } "NODE_NAME" } } { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "24.000 ns ( 85.71 % ) " "Info: Total cell delay = 24.000 ns ( 85.71 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 14.29 % ) " "Info: Total interconnect delay = 4.000 ns ( 14.29 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "28.000 ns" { d[0] Mux4~141 next_state[0]~40 current_state[0] } "NODE_NAME" } } { "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "28.000 ns" { d[0] d[0]~out Mux4~141 next_state[0]~40 current_state[0] } { 0.000ns 0.000ns 2.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 7.000ns 9.000ns 6.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" { } { { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 15 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 6 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clk'" { } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns current_state\[0\] 2 REG LC12 12 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC12; Fanout = 12; REG Node = 'current_state\[0\]'" { } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { clk current_state[0] } "NODE_NAME" } } { "../shixu/zhuangtai.vhd" "" { Text "E:/Quartus II LAB/shixu/zhuangtai.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk current_state[0] } "NODE_NAME" } } { "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out current_state[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "28.000 ns" { d[0] Mux4~141 next_state[0]~40 current_state[0] } "NODE_NAME" } } { "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "28.000 ns" { d[0] d[0]~out Mux4~141 next_state[0]~40 current_state[0] } { 0.000ns 0.000ns 2.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 7.000ns 9.000ns 6.000ns } "" } } { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk current_state[0] } "NODE_NAME" } } { "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out current_state[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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