📄 zhuangtai.fit.rpt
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+------+----------+---------+----------------------+------------------+
+---------------------------------+
; Non-Global High Fan-Out Signals ;
+------------------+--------------+
; Name ; Fan-Out ;
+------------------+--------------+
; rst ; 6 ;
; current_state[0] ; 6 ;
; current_state[1] ; 4 ;
; Mux4~141 ; 3 ;
; next_state[0]~40 ; 2 ;
; current_state[2] ; 2 ;
; next_state[2]~33 ; 2 ;
; next_state[1]~26 ; 2 ;
; Mux2~8 ; 2 ;
; d[1] ; 1 ;
; d[0] ; 1 ;
; Mux1~27sexp ; 1 ;
; ~GND~0 ; 1 ;
; y[0]~reg0 ; 1 ;
; y[2]~reg0 ; 1 ;
; y[1]~reg0 ; 1 ;
+------------------+--------------+
+-----------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+------------------+
; Output enables ; 0 / 6 ( 0 % ) ;
; PIA buffers ; 11 / 288 ( 4 % ) ;
; PIAs ; 11 / 288 ( 4 % ) ;
+----------------------------+------------------+
+----------------------------------------------------------------------------+
; LAB External Interconnect ;
+----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 1.38) ; Number of LABs (Total = 1) ;
+----------------------------------------------+-----------------------------+
; 0 ; 7 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 1 ;
+----------------------------------------------+-----------------------------+
+----------------------------------------------------------------------+
; LAB Macrocells ;
+----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 1.50) ; Number of LABs (Total = 1) ;
+----------------------------------------+-----------------------------+
; 0 ; 7 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 1 ;
+----------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------+
; Shareable Expander ;
+-------------------------------------------------+-----------------------------+
; Number of shareable expanders (Average = 0.13) ; Number of LABs (Total = 1) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 7 ;
; 1 ; 1 ;
+-------------------------------------------------+-----------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+------------------------------------------------------------------+------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+------------------------------------------------------------------+------------------------------------------------------------------------------+
; A ; LC1 ; current_state[0], current_state[1] ; y[1]~reg0, next_state[1]~26 ;
; A ; LC3 ; clk, Mux2~8, rst ; y[1] ;
; A ; LC2 ; Mux2~8, Mux4~141, next_state[1]~26 ; next_state[1]~26, current_state[1] ;
; A ; LC4 ; clk, next_state[1]~26, rst ; Mux2~8, Mux4~141, next_state[2]~33, Mux1~27sexp ;
; A ; LC7 ; Mux4~141, next_state[2]~33, current_state[0], current_state[1] ; next_state[2]~33, current_state[2] ;
; A ; LC9 ; clk, next_state[2]~33, rst ; y[2]~reg0, Mux4~141 ;
; A ; LC5 ; clk, current_state[2], rst, Mux1~27sexp ; y[2] ;
; A ; LC10 ; current_state[1], d[1], d[0], current_state[2], current_state[0] ; next_state[1]~26, next_state[2]~33, next_state[0]~40 ;
; A ; LC11 ; current_state[0], Mux4~141, next_state[0]~40 ; next_state[0]~40, current_state[0] ;
; A ; LC12 ; clk, next_state[0]~40, rst ; Mux2~8, Mux4~141, next_state[0]~40, y[0]~reg0, next_state[2]~33, Mux1~27sexp ;
; A ; LC6 ; clk, current_state[0], rst ; y[0] ;
; A ; LC8 ; ; y[3] ;
+-----+------------+------------------------------------------------------------------+------------------------------------------------------------------------------+
+----------------------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+-----------------------------------------+
; Option ; Setting ;
+----------------------------------------------+-----------------------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Reserve all unused pins ; As output driving an unspecified signal ;
; Security bit ; Off ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+-----------------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Fri Oct 26 20:42:17 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off zhuangtai -c zhuangtai
Info: Selected device EPM7128SLC84-15 for design "zhuangtai"
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Allocated 127 megabytes of memory during processing
Info: Processing ended: Fri Oct 26 20:42:18 2007
Info: Elapsed time: 00:00:01
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