zhuangtai.tan.rpt

状态机的典型饮用

; N/A   ; None         ; 29.000 ns  ; d[1] ; current_state[2] ; clk      ;
; N/A   ; None         ; 29.000 ns  ; d[1] ; current_state[1] ; clk      ;
; N/A   ; None         ; 11.000 ns  ; rst  ; y[1]~reg0        ; clk      ;
; N/A   ; None         ; 11.000 ns  ; rst  ; y[2]~reg0        ; clk      ;
; N/A   ; None         ; 11.000 ns  ; rst  ; y[0]~reg0        ; clk      ;
+-------+--------------+------------+------+------------------+----------+


+-------------------------------------------------------------------+
; tco                                                               ;
+-------+--------------+------------+-----------+------+------------+
; Slack ; Required tco ; Actual tco ; From      ; To   ; From Clock ;
+-------+--------------+------------+-----------+------+------------+
; N/A   ; None         ; 8.000 ns   ; y[0]~reg0 ; y[0] ; clk        ;
; N/A   ; None         ; 8.000 ns   ; y[2]~reg0 ; y[2] ; clk        ;
; N/A   ; None         ; 8.000 ns   ; y[1]~reg0 ; y[1] ; clk        ;
+-------+--------------+------------+-----------+------+------------+


+-------------------------------------------------------------------------------+
; th                                                                            ;
+---------------+-------------+------------+------+------------------+----------+
; Minimum Slack ; Required th ; Actual th  ; From ; To               ; To Clock ;
+---------------+-------------+------------+------+------------------+----------+
; N/A           ; None        ; -3.000 ns  ; rst  ; y[1]~reg0        ; clk      ;
; N/A           ; None        ; -3.000 ns  ; rst  ; y[2]~reg0        ; clk      ;
; N/A           ; None        ; -3.000 ns  ; rst  ; y[0]~reg0        ; clk      ;
; N/A           ; None        ; -21.000 ns ; d[0] ; current_state[0] ; clk      ;
; N/A           ; None        ; -21.000 ns ; d[0] ; current_state[2] ; clk      ;
; N/A           ; None        ; -21.000 ns ; d[0] ; current_state[1] ; clk      ;
; N/A           ; None        ; -21.000 ns ; d[1] ; current_state[0] ; clk      ;
; N/A           ; None        ; -21.000 ns ; d[1] ; current_state[2] ; clk      ;
; N/A           ; None        ; -21.000 ns ; d[1] ; current_state[1] ; clk      ;
+---------------+-------------+------------+------+------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Fri Oct 26 20:42:26 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off zhuangtai -c zhuangtai
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found combinational loop of 1 nodes
    Warning: Node "next_state[1]~26"
Warning: Found combinational loop of 1 nodes
    Warning: Node "next_state[2]~33"
Warning: Found combinational loop of 1 nodes
    Warning: Node "next_state[0]~40"
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 32.26 MHz between source register "current_state[0]" and destination register "current_state[0]" (period= 31.0 ns)
    Info: + Longest register to register delay is 26.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC12; Fanout = 12; REG Node = 'current_state[0]'
        Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC10; Fanout = 9; COMB Node = 'Mux4~141'
        Info: 3: + IC(0.000 ns) + CELL(9.000 ns) = 18.000 ns; Loc. = LC11; Fanout = 3; COMB LOOP Node = 'next_state[0]~40'
            Info: Loc. = LC11; Node "next_state[0]~40"
        Info: 4: + IC(2.000 ns) + CELL(6.000 ns) = 26.000 ns; Loc. = LC12; Fanout = 12; REG Node = 'current_state[0]'
        Info: Total cell delay = 22.000 ns ( 84.62 % )
        Info: Total interconnect delay = 4.000 ns ( 15.38 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC12; Fanout = 12; REG Node = 'current_state[0]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
        Info: - Longest clock path from clock "clk" to source register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC12; Fanout = 12; REG Node = 'current_state[0]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: tsu for register "current_state[0]" (data pin = "d[0]", clock pin = "clk") is 29.000 ns
    Info: + Longest pin to register delay is 28.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_4; Fanout = 3; PIN Node = 'd[0]'
        Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC10; Fanout = 9; COMB Node = 'Mux4~141'
        Info: 3: + IC(0.000 ns) + CELL(9.000 ns) = 20.000 ns; Loc. = LC11; Fanout = 3; COMB LOOP Node = 'next_state[0]~40'
            Info: Loc. = LC11; Node "next_state[0]~40"
        Info: 4: + IC(2.000 ns) + CELL(6.000 ns) = 28.000 ns; Loc. = LC12; Fanout = 12; REG Node = 'current_state[0]'
        Info: Total cell delay = 24.000 ns ( 85.71 % )
        Info: Total interconnect delay = 4.000 ns ( 14.29 % )
    Info: + Micro setup delay of destination is 4.000 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC12; Fanout = 12; REG Node = 'current_state[0]'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: tco from clock "clk" to destination pin "y[0]" through register "y[0]~reg0" is 8.000 ns
    Info: + Longest clock path from clock "clk" to source register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC6; Fanout = 1; REG Node = 'y[0]~reg0'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Longest register to pin delay is 4.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6; Fanout = 1; REG Node = 'y[0]~reg0'
        Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_10; Fanout = 0; PIN Node = 'y[0]'
        Info: Total cell delay = 4.000 ns ( 100.00 % )
Info: th for register "y[1]~reg0" (data pin = "rst", clock pin = "clk") is -3.000 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 1; REG Node = 'y[1]~reg0'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 4.000 ns
    Info: - Shortest pin to register delay is 10.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_33; Fanout = 6; PIN Node = 'rst'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC3; Fanout = 1; REG Node = 'y[1]~reg0'
        Info: Total cell delay = 8.000 ns ( 80.00 % )
        Info: Total interconnect delay = 2.000 ns ( 20.00 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 8 warnings
    Info: Allocated 97 megabytes of memory during processing
    Info: Processing ended: Fri Oct 26 20:42:27 2007
    Info: Elapsed time: 00:00:01