or_1.vhd

来自「全加器」· VHDL 代码 · 共 11 行

library ieee;
use ieee.std_logic_1164.all;

entity or_1 is
port(in_a,in_b:    in    std_logic;
     out_or:       out   std_logic);
end or_1;
architecture first of or_1 is
begin
out_or<=in_a or in_b;
end first;