banjia.vhd

全加器

library ieee;
use ieee.std_logic_1164.all;

entity banjia is
port(in_a,in_b:     in     std_logic;
     out_s,out_c:   out    std_logic);
end banjia;
architecture first of banjia is
begin
out_s<=not(in_a xor not(in_b));
out_c<=in_a and in_b;
end first;