quanjia.vhd

全加器

-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 7.0 Build 33 02/05/2007 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY quanjia IS 
	port
	(
		ain :  IN  STD_LOGIC;
		bin :  IN  STD_LOGIC;
		cin :  IN  STD_LOGIC;
		count :  OUT  STD_LOGIC;
		sum :  OUT  STD_LOGIC
	);
END quanjia;

ARCHITECTURE bdf_type OF quanjia IS 

component banjia
	PORT(in_a : IN STD_LOGIC;
		 in_b : IN STD_LOGIC;
		 out_s : OUT STD_LOGIC;
		 out_c : OUT STD_LOGIC
	);
end component;

signal	SYNTHESIZED_WIRE_0 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_1 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_2 :  STD_LOGIC;


BEGIN 



b2v_inst : banjia
PORT MAP(in_a => ain,
		 in_b => bin,
		 out_s => SYNTHESIZED_WIRE_0,
		 out_c => SYNTHESIZED_WIRE_2);

b2v_inst10 : banjia
PORT MAP(in_a => SYNTHESIZED_WIRE_0,
		 in_b => cin,
		 out_s => sum,
		 out_c => SYNTHESIZED_WIRE_1);

count <= SYNTHESIZED_WIRE_1 OR SYNTHESIZED_WIRE_2;

END;