fenpin.tan.rpt

分频器

; Clock Setup: 'clk_in'                                                                                                                                                                                                ;
+-------+----------------------------------+-------------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)             ; From                          ; To                            ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+----------------------------------+-------------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:aqi_rtl_0|dffs[0] ; lpm_counter:aqi_rtl_0|dffs[0] ; clk_in     ; clk_in   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:aqi_rtl_0|dffs[3] ; lpm_counter:aqi_rtl_0|dffs[0] ; clk_in     ; clk_in   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:aqi_rtl_0|dffs[2] ; lpm_counter:aqi_rtl_0|dffs[0] ; clk_in     ; clk_in   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:aqi_rtl_0|dffs[1] ; lpm_counter:aqi_rtl_0|dffs[0] ; clk_in     ; clk_in   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:aqi_rtl_0|dffs[0] ; lpm_counter:aqi_rtl_0|dffs[3] ; clk_in     ; clk_in   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:aqi_rtl_0|dffs[3] ; lpm_counter:aqi_rtl_0|dffs[3] ; clk_in     ; clk_in   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:aqi_rtl_0|dffs[2] ; lpm_counter:aqi_rtl_0|dffs[3] ; clk_in     ; clk_in   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:aqi_rtl_0|dffs[1] ; lpm_counter:aqi_rtl_0|dffs[3] ; clk_in     ; clk_in   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:aqi_rtl_0|dffs[0] ; lpm_counter:aqi_rtl_0|dffs[2] ; clk_in     ; clk_in   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:aqi_rtl_0|dffs[3] ; lpm_counter:aqi_rtl_0|dffs[2] ; clk_in     ; clk_in   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:aqi_rtl_0|dffs[2] ; lpm_counter:aqi_rtl_0|dffs[2] ; clk_in     ; clk_in   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:aqi_rtl_0|dffs[1] ; lpm_counter:aqi_rtl_0|dffs[2] ; clk_in     ; clk_in   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:aqi_rtl_0|dffs[0] ; lpm_counter:aqi_rtl_0|dffs[1] ; clk_in     ; clk_in   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:aqi_rtl_0|dffs[3] ; lpm_counter:aqi_rtl_0|dffs[1] ; clk_in     ; clk_in   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:aqi_rtl_0|dffs[2] ; lpm_counter:aqi_rtl_0|dffs[1] ; clk_in     ; clk_in   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:aqi_rtl_0|dffs[1] ; lpm_counter:aqi_rtl_0|dffs[1] ; clk_in     ; clk_in   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:aqi_rtl_0|dffs[3] ; clk_out~reg0                  ; clk_in     ; clk_in   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:aqi_rtl_0|dffs[2] ; clk_out~reg0                  ; clk_in     ; clk_in   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:aqi_rtl_0|dffs[1] ; clk_out~reg0                  ; clk_in     ; clk_in   ; None                        ; None                      ; 8.000 ns                ;
+-------+----------------------------------+-------------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------------+
; tco                                                                     ;
+-------+--------------+------------+--------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To      ; From Clock ;
+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 8.000 ns   ; clk_out~reg0 ; clk_out ; clk_in     ;
+-------+--------------+------------+--------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Tue Oct 23 22:38:32 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off fenpin -c fenpin
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk_in" is an undefined clock
Info: Clock "clk_in" has Internal fmax of 76.92 MHz between source register "lpm_counter:aqi_rtl_0|dffs[0]" and destination register "lpm_counter:aqi_rtl_0|dffs[0]" (period= 13.0 ns)
    Info: + Longest register to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 7; REG Node = 'lpm_counter:aqi_rtl_0|dffs[0]'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC1; Fanout = 7; REG Node = 'lpm_counter:aqi_rtl_0|dffs[0]'
        Info: Total cell delay = 6.000 ns ( 75.00 % )
        Info: Total interconnect delay = 2.000 ns ( 25.00 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk_in" to destination register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 5; CLK Node = 'clk_in'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC1; Fanout = 7; REG Node = 'lpm_counter:aqi_rtl_0|dffs[0]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
        Info: - Longest clock path from clock "clk_in" to source register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 5; CLK Node = 'clk_in'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC1; Fanout = 7; REG Node = 'lpm_counter:aqi_rtl_0|dffs[0]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: tco from clock "clk_in" to destination pin "clk_out" through register "clk_out~reg0" is 8.000 ns
    Info: + Longest clock path from clock "clk_in" to source register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 5; CLK Node = 'clk_in'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 1; REG Node = 'clk_out~reg0'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Longest register to pin delay is 4.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 1; REG Node = 'clk_out~reg0'
        Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'clk_out'
        Info: Total cell delay = 4.000 ns ( 100.00 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Allocated 97 megabytes of memory during processing
    Info: Processing ended: Tue Oct 23 22:38:32 2007
    Info: Elapsed time: 00:00:00