📄 fenpin.fit.rpt
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; 54 ; 53 ; -- ; RESERVED ; ; ; ; ;
; 55 ; 54 ; -- ; RESERVED ; ; ; ; ;
; 56 ; 55 ; -- ; RESERVED ; ; ; ; ;
; 57 ; 56 ; -- ; RESERVED ; ; ; ; ;
; 58 ; 57 ; -- ; RESERVED ; ; ; ; ;
; 59 ; 58 ; -- ; GND ; gnd ; ; ; ;
; 60 ; 59 ; -- ; RESERVED ; ; ; ; ;
; 61 ; 60 ; -- ; RESERVED ; ; ; ; ;
; 62 ; 61 ; -- ; TCK ; input ; TTL ; ; N ;
; 63 ; 62 ; -- ; RESERVED ; ; ; ; ;
; 64 ; 63 ; -- ; RESERVED ; ; ; ; ;
; 65 ; 64 ; -- ; RESERVED ; ; ; ; ;
; 66 ; 65 ; -- ; VCCIO ; power ; ; 5.0V ; ;
; 67 ; 66 ; -- ; RESERVED ; ; ; ; ;
; 68 ; 67 ; -- ; RESERVED ; ; ; ; ;
; 69 ; 68 ; -- ; RESERVED ; ; ; ; ;
; 70 ; 69 ; -- ; RESERVED ; ; ; ; ;
; 71 ; 70 ; -- ; TDO ; output ; TTL ; ; N ;
; 72 ; 71 ; -- ; GND ; gnd ; ; ; ;
; 73 ; 72 ; -- ; RESERVED ; ; ; ; ;
; 74 ; 73 ; -- ; RESERVED ; ; ; ; ;
; 75 ; 74 ; -- ; RESERVED ; ; ; ; ;
; 76 ; 75 ; -- ; RESERVED ; ; ; ; ;
; 77 ; 76 ; -- ; RESERVED ; ; ; ; ;
; 78 ; 77 ; -- ; VCCIO ; power ; ; 5.0V ; ;
; 79 ; 78 ; -- ; RESERVED ; ; ; ; ;
; 80 ; 79 ; -- ; RESERVED ; ; ; ; ;
; 81 ; 80 ; -- ; RESERVED ; ; ; ; ;
; 82 ; 81 ; -- ; GND ; gnd ; ; ; ;
; 83 ; 82 ; -- ; clk_in ; input ; TTL ; ; N ;
; 84 ; 83 ; -- ; GND+ ; ; ; ; ;
+----------+------------+----------+----------------+--------+--------------+---------+-----------------+
+--------------------------------------------------------------------------------------------------+
; I/O Standard ;
+--------------+------------+----------------------+-------------------+-------------------+-------+
; I/O Standard ; Input Vref ; Dedicated Input Pins ; Pins in I/O Bank1 ; Pins in I/O Bank2 ; Total ;
+--------------+------------+----------------------+-------------------+-------------------+-------+
; TTL ; - ; 1 ; 0 ; 0 ; 1 ;
+--------------+------------+----------------------+-------------------+-------------------+-------+
+----------------------------------------------------------------------+
; Dedicated Inputs I/O ;
+--------+-------+-------+-------+--------------+------------+---------+
; Name ; Pin # ; Type ; VCCIO ; I/O Standard ; Input Vref ; Current ;
+--------+-------+-------+-------+--------------+------------+---------+
; clk_in ; 83 ; Input ; -- ; TTL ; - ; 0 mA ;
+--------+-------+-------+-------+--------------+------------+---------+
+-----------------------------------------------+
; Output Pin Default Load For Reported TCO ;
+--------------+-------+------------------------+
; I/O Standard ; Load ; Termination Resistance ;
+--------------+-------+------------------------+
; 3.3-V LVTTL ; 10 pF ; Not Available ;
; 3.3-V LVCMOS ; 10 pF ; Not Available ;
; TTL ; 10 pF ; Not Available ;
+--------------+-------+------------------------+
Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
+--------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity ;
+----------------------------+------------+------+-------------------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+-------------------------------+
; |fenpin ; 5 ; 6 ; |fenpin ;
; |lpm_counter:aqi_rtl_0| ; 4 ; 0 ; |fenpin|lpm_counter:aqi_rtl_0 ;
+----------------------------+------------+------+-------------------------------+
+----------------------------------------------------------------------------------------+
; Control Signals ;
+--------+----------+---------+-------+--------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+--------+----------+---------+-------+--------+----------------------+------------------+
; clk_in ; PIN_83 ; 5 ; Clock ; yes ; On ; -- ;
+--------+----------+---------+-------+--------+----------------------+------------------+
+-----------------------------------------------------------------------+
; Global & Other Fast Signals ;
+--------+----------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+--------+----------+---------+----------------------+------------------+
; clk_in ; PIN_83 ; 5 ; On ; -- ;
+--------+----------+---------+----------------------+------------------+
+-----------------------------------------+
; Non-Global High Fan-Out Signals ;
+-------------------------------+---------+
; Name ; Fan-Out ;
+-------------------------------+---------+
; lpm_counter:aqi_rtl_0|dffs[3] ; 5 ;
; lpm_counter:aqi_rtl_0|dffs[2] ; 5 ;
; lpm_counter:aqi_rtl_0|dffs[1] ; 5 ;
; lpm_counter:aqi_rtl_0|dffs[0] ; 4 ;
; clk_out~reg0 ; 1 ;
+-------------------------------+---------+
+----------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+-----------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+-----------------+
; Output enables ; 0 / 6 ( 0 % ) ;
; PIA buffers ; 4 / 288 ( 1 % ) ;
; PIAs ; 4 / 288 ( 1 % ) ;
+----------------------------+-----------------+
+----------------------------------------------------------------------------+
; LAB External Interconnect ;
+----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 0.50) ; Number of LABs (Total = 1) ;
+----------------------------------------------+-----------------------------+
; 0 ; 7 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 1 ;
+----------------------------------------------+-----------------------------+
+----------------------------------------------------------------------+
; LAB Macrocells ;
+----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 0.63) ; Number of LABs (Total = 1) ;
+----------------------------------------+-----------------------------+
; 0 ; 7 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 1 ;
+----------------------------------------+-----------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC1 ; clk_in, lpm_counter:aqi_rtl_0|dffs[3], lpm_counter:aqi_rtl_0|dffs[0], lpm_counter:aqi_rtl_0|dffs[2], lpm_counter:aqi_rtl_0|dffs[1] ; lpm_counter:aqi_rtl_0|dffs[0], lpm_counter:aqi_rtl_0|dffs[1], lpm_counter:aqi_rtl_0|dffs[2], lpm_counter:aqi_rtl_0|dffs[3] ;
; A ; LC2 ; clk_in, lpm_counter:aqi_rtl_0|dffs[3], lpm_counter:aqi_rtl_0|dffs[1], lpm_counter:aqi_rtl_0|dffs[0], lpm_counter:aqi_rtl_0|dffs[2] ; lpm_counter:aqi_rtl_0|dffs[0], lpm_counter:aqi_rtl_0|dffs[1], lpm_counter:aqi_rtl_0|dffs[2], lpm_counter:aqi_rtl_0|dffs[3], clk_out~reg0 ;
; A ; LC4 ; clk_in, lpm_counter:aqi_rtl_0|dffs[3], lpm_counter:aqi_rtl_0|dffs[1], lpm_counter:aqi_rtl_0|dffs[0], lpm_counter:aqi_rtl_0|dffs[2] ; lpm_counter:aqi_rtl_0|dffs[0], lpm_counter:aqi_rtl_0|dffs[1], lpm_counter:aqi_rtl_0|dffs[2], lpm_counter:aqi_rtl_0|dffs[3], clk_out~reg0 ;
; A ; LC5 ; clk_in, lpm_counter:aqi_rtl_0|dffs[2], lpm_counter:aqi_rtl_0|dffs[1], lpm_counter:aqi_rtl_0|dffs[3], lpm_counter:aqi_rtl_0|dffs[0] ; lpm_counter:aqi_rtl_0|dffs[0], lpm_counter:aqi_rtl_0|dffs[1], lpm_counter:aqi_rtl_0|dffs[2], lpm_counter:aqi_rtl_0|dffs[3], clk_out~reg0 ;
; A ; LC3 ; clk_in, lpm_counter:aqi_rtl_0|dffs[2], lpm_counter:aqi_rtl_0|dffs[1], lpm_counter:aqi_rtl_0|dffs[3] ; clk_out ;
+-----+------------+------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------+
+----------------------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+-----------------------------------------+
; Option ; Setting ;
+----------------------------------------------+-----------------------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Reserve all unused pins ; As output driving an unspecified signal ;
; Security bit ; Off ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+-----------------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Tue Oct 23 22:38:24 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off fenpin -c fenpin
Info: Selected device EPM7128SLC84-15 for design "fenpin"
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Allocated 127 megabytes of memory during processing
Info: Processing ended: Tue Oct 23 22:38:24 2007
Info: Elapsed time: 00:00:00
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