📄 jkchu.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register q~reg0 register q~reg0 76.92 MHz 13.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 76.92 MHz between source register \"q~reg0\" and destination register \"q~reg0\" (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q~reg0 1 REG LC3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 4; REG Node = 'q~reg0'" { } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { q~reg0 } "NODE_NAME" } } { "jkchu.vhd" "" { Text "E:/Quartus II LAB/jkchu/jkchu.vhd" 16 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns q~reg0 2 REG LC3 4 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC3; Fanout = 4; REG Node = 'q~reg0'" { } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { q~reg0 q~reg0 } "NODE_NAME" } } { "jkchu.vhd" "" { Text "E:/Quartus II LAB/jkchu/jkchu.vhd" 16 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns ( 75.00 % ) " "Info: Total cell delay = 6.000 ns ( 75.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 25.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { q~reg0 q~reg0 } "NODE_NAME" } } { "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "8.000 ns" { q~reg0 q~reg0 } { 0.000ns 2.000ns } { 0.000ns 6.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 1 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 1; CLK Node = 'clk'" { } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jkchu.vhd" "" { Text "E:/Quartus II LAB/jkchu/jkchu.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns q~reg0 2 REG LC3 4 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 4; REG Node = 'q~reg0'" { } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { clk q~reg0 } "NODE_NAME" } } { "jkchu.vhd" "" { Text "E:/Quartus II LAB/jkchu/jkchu.vhd" 16 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk q~reg0 } "NODE_NAME" } } { "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out q~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 1 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 1; CLK Node = 'clk'" { } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jkchu.vhd" "" { Text "E:/Quartus II LAB/jkchu/jkchu.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns q~reg0 2 REG LC3 4 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 4; REG Node = 'q~reg0'" { } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { clk q~reg0 } "NODE_NAME" } } { "jkchu.vhd" "" { Text "E:/Quartus II LAB/jkchu/jkchu.vhd" 16 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk q~reg0 } "NODE_NAME" } } { "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out q~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk q~reg0 } "NODE_NAME" } } { "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out q~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } } { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk q~reg0 } "NODE_NAME" } } { "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out q~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "jkchu.vhd" "" { Text "E:/Quartus II LAB/jkchu/jkchu.vhd" 16 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" { } { { "jkchu.vhd" "" { Text "E:/Quartus II LAB/jkchu/jkchu.vhd" 16 0 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { q~reg0 q~reg0 } "NODE_NAME" } } { "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "8.000 ns" { q~reg0 q~reg0 } { 0.000ns 2.000ns } { 0.000ns 6.000ns } "" } } { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk q~reg0 } "NODE_NAME" } } { "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out q~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } } { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk q~reg0 } "NODE_NAME" } } { "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out q~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "q~reg0 j clk 11.000 ns register " "Info: tsu for register \"q~reg0\" (data pin = \"j\", clock pin = \"clk\") is 11.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns + Longest pin register " "Info: + Longest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns j 1 PIN PIN_33 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_33; Fanout = 1; PIN Node = 'j'" { } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { j } "NODE_NAME" } } { "jkchu.vhd" "" { Text "E:/Quartus II LAB/jkchu/jkchu.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns q~reg0 2 REG LC3 4 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC3; Fanout = 4; REG Node = 'q~reg0'" { } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { j q~reg0 } "NODE_NAME" } } { "jkchu.vhd" "" { Text "E:/Quartus II LAB/jkchu/jkchu.vhd" 16 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns ( 80.00 % ) " "Info: Total cell delay = 8.000 ns ( 80.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 20.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { j q~reg0 } "NODE_NAME" } } { "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { j j~out q~reg0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" { } { { "jkchu.vhd" "" { Text "E:/Quartus II LAB/jkchu/jkchu.vhd" 16 0 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 1 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 1; CLK Node = 'clk'" { } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jkchu.vhd" "" { Text "E:/Quartus II LAB/jkchu/jkchu.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns q~reg0 2 REG LC3 4 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 4; REG Node = 'q~reg0'" { } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { clk q~reg0 } "NODE_NAME" } } { "jkchu.vhd" "" { Text "E:/Quartus II LAB/jkchu/jkchu.vhd" 16 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk q~reg0 } "NODE_NAME" } } { "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out q~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { j q~reg0 } "NODE_NAME" } } { "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { j j~out q~reg0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } } { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk q~reg0 } "NODE_NAME" } } { "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out q~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk qbar q~reg0 17.000 ns register " "Info: tco from clock \"clk\" to destination pin \"qbar\" through register \"q~reg0\" is 17.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 1 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 1; CLK Node = 'clk'" { } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jkchu.vhd" "" { Text "E:/Quartus II LAB/jkchu/jkchu.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns q~reg0 2 REG LC3 4 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 4; REG Node = 'q~reg0'" { } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { clk q~reg0 } "NODE_NAME" } } { "jkchu.vhd" "" { Text "E:/Quartus II LAB/jkchu/jkchu.vhd" 16 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk q~reg0 } "NODE_NAME" } } { "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out q~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "jkchu.vhd" "" { Text "E:/Quartus II LAB/jkchu/jkchu.vhd" 16 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.000 ns + Longest register pin " "Info: + Longest register to pin delay is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q~reg0 1 REG LC3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 4; REG Node = 'q~reg0'" { } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { q~reg0 } "NODE_NAME" } } { "jkchu.vhd" "" { Text "E:/Quartus II LAB/jkchu/jkchu.vhd" 16 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns q~3 2 COMB LC5 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC5; Fanout = 1; COMB Node = 'q~3'" { } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "9.000 ns" { q~reg0 q~3 } "NODE_NAME" } } { "jkchu.vhd" "" { Text "E:/Quartus II LAB/jkchu/jkchu.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 13.000 ns qbar 3 PIN PIN_11 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'qbar'" { } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { q~3 qbar } "NODE_NAME" } } { "jkchu.vhd" "" { Text "E:/Quartus II LAB/jkchu/jkchu.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.000 ns ( 84.62 % ) " "Info: Total cell delay = 11.000 ns ( 84.62 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 15.38 % ) " "Info: Total interconnect delay = 2.000 ns ( 15.38 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "13.000 ns" { q~reg0 q~3 qbar } "NODE_NAME" } } { "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "13.000 ns" { q~reg0 q~3 qbar } { 0.000ns 2.000ns 0.000ns } { 0.000ns 7.000ns 4.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk q~reg0 } "NODE_NAME" } } { "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out q~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } } { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "13.000 ns" { q~reg0 q~3 qbar } "NODE_NAME" } } { "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "13.000 ns" { q~reg0 q~3 qbar } { 0.000ns 2.000ns 0.000ns } { 0.000ns 7.000ns 4.000ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "q~reg0 j clk -3.000 ns register " "Info: th for register \"q~reg0\" (data pin = \"j\", clock pin = \"clk\") is -3.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 1 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 1; CLK Node = 'clk'" { } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jkchu.vhd" "" { Text "E:/Quartus II LAB/jkchu/jkchu.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns q~reg0 2 REG LC3 4 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 4; REG Node = 'q~reg0'" { } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { clk q~reg0 } "NODE_NAME" } } { "jkchu.vhd" "" { Text "E:/Quartus II LAB/jkchu/jkchu.vhd" 16 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk q~reg0 } "NODE_NAME" } } { "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out q~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" { } { { "jkchu.vhd" "" { Text "E:/Quartus II LAB/jkchu/jkchu.vhd" 16 0 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns j 1 PIN PIN_33 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_33; Fanout = 1; PIN Node = 'j'" { } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { j } "NODE_NAME" } } { "jkchu.vhd" "" { Text "E:/Quartus II LAB/jkchu/jkchu.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns q~reg0 2 REG LC3 4 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC3; Fanout = 4; REG Node = 'q~reg0'" { } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { j q~reg0 } "NODE_NAME" } } { "jkchu.vhd" "" { Text "E:/Quartus II LAB/jkchu/jkchu.vhd" 16 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns ( 80.00 % ) " "Info: Total cell delay = 8.000 ns ( 80.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 20.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { j q~reg0 } "NODE_NAME" } } { "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { j j~out q~reg0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk q~reg0 } "NODE_NAME" } } { "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out q~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } } { "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/7.0/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { j q~reg0 } "NODE_NAME" } } { "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/7.0/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { j j~out q~reg0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "97 " "Info: Allocated 97 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 25 16:47:02 2007 " "Info: Processing ended: Thu Oct 25 16:47:02 2007" { } { } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
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