jkchu.vhd

来自「jk触发器」· VHDL 代码 · 共 30 行

library ieee;
use ieee.std_logic_1164.all;

entity jkchu is
port(j,k:   in    std_logic;
     clk:   in    std_logic;
     q:     buffer std_logic;
     qbar:  out std_logic);
end entity;
architecture first of jkchu is
signal x: std_logic_vector(1 downto 0);
begin
x<=j & k;
process(clk,q)
begin
if(clk'event and clk='1' and clk'last_value='0') then
case x is
   when "10" => q<=j;

   when "01" => q<=j;

   when "00" => q<=not q'last_value;

   when "11" => q<=q'last_value;

end case;
end if;
   qbar<= not q;
end process;
end first;