graycode.fit.rpt

二进制码转换为格雷码

Fitter report for GRAYcode
Sun Mar 13 21:56:05 2005
Version 4.0 Build 190 1/28/2004 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Device Options
  5. Fitter Equations
  6. Floorplan View
  7. Pin-Out File
  8. Fitter Resource Usage Summary
  9. Input Pins
 10. Output Pins
 11. All Package Pins
 12. Output Pin Load For Reported TCO
 13. Fitter Resource Utilization by Entity
 14. Non-Global High Fan-Out Signals
 15. Interconnect Usage Summary
 16. LAB Macrocells
 17. Logic Cell Interconnection
 18. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+---------------------------------------------------------------+
; Fitter Summary                                                ;
+-----------------------+---------------------------------------+
; Fitter Status         ; Successful - Sun Mar 13 21:56:05 2005 ;
; Revision Name         ; GRAYcode                              ;
; Top-level Entity Name ; GRAYcode                              ;
; Family                ; MAX3000A                              ;
; Device                ; EPM3032ALC44-4                        ;
; Total macrocells      ; 5 / 32 ( 15 % )                       ;
; Total pins            ; 14 / 34 ( 41 % )                      ;
+-----------------------+---------------------------------------+


+--------------------------------------------------------------------------------------+
; Fitter Settings                                                                      ;
+---------------------------------------------------------------------------------------
; Option                                     ; Setting            ; Default Value      ;
+--------------------------------------------+--------------------+--------------------+
; Device                                     ; AUTO               ;                    ;
; Slow Slew Rate                             ; Off                ; Off                ;
; Fitter Initial Placement Seed              ; 1                  ; 1                  ;
; FIT_ONLY_ONE_ATTEMPT                       ; Off                ; Off                ;
; Optimize IOC Register Placement for Timing ; On                 ; On                 ;
; Optimize Timing                            ; Normal Compilation ; Normal Compilation ;
+--------------------------------------------+--------------------+--------------------+


+-------------------------------------------------------------------------+
; Fitter Device Options                                                   ;
+--------------------------------------------------------------------------
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Auto-restart configuration after error       ; On                       ;
; Release clears before tri-states             ; Off                      ;
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Reserve all unused pins                      ; As output driving ground ;
; Security bit                                 ; Off                      ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+-------------------+
; Fitter Equations  ;
+-------------------+
The equations can be found in d:/工作目录/2_人民邮电刘浩/选题3--cpld实例导航/文档目录/第3章 ing/graycode/GRAYcode.fit.eqn.


+-----------------+
; Floorplan View  ;
+-----------------+
Floorplan report data cannot be output to ASCII.
Please use Quartus II to view the floorplan report data.


+---------------+
; Pin-Out File  ;
+---------------+
The pin-out file can be found in d:/工作目录/2_人民邮电刘浩/选题3--cpld实例导航/文档目录/第3章 ing/graycode/GRAYcode.pin.


+-------------------------------------------------+
; Fitter Resource Usage Summary                   ;
+--------------------------------------------------
; Resource                     ; Usage            ;
+------------------------------+------------------+
; Logic cells                  ; 5 / 32 ( 15 % )  ;
; Registers                    ; 0 / 32 ( 0 % )   ;
; Number of pterms used        ; 19               ;
; User inserted logic cells    ; 0                ;
; I/O pins                     ; 14 / 34 ( 41 % ) ;
;     -- Clock pins            ; 0 / 2 ( 0 % )    ;
;     -- Dedicated input pins  ; 0 / 2 ( 0 % )    ;
; Global signals               ; 0                ;
; Shareable expanders          ; 0 / 32 ( 0 % )   ;
; Parallel expanders           ; 0 / 30 ( 0 % )   ;
; Cells using turbo bit        ; 5 / 32 ( 15 % )  ;
; Maximum fan-out node         ; EN               ;
; Maximum fan-out              ; 5                ;
; Total fan-out                ; 21               ;
; Average fan-out              ; 1.11             ;
+------------------------------+------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                      ;
+----------------------------------------------------------------------------------------------------------------------------------
; Name       ; Pin # ; I/O Bank ; LAB ; Combinational Fan-Out ; Registered Fan-Out ; Global ; I/O Standard ; Location assigned by ;
+------------+-------+----------+-----+-----------------------+--------------------+--------+--------------+----------------------+
; EN         ; 24    ; --       ; 2   ; 5                     ; 0                  ; no     ; LVTTL        ; Fitter               ;
; data_in[0] ; 16    ; --       ; 1   ; 1                     ; 0                  ; no     ; LVTTL        ; Fitter               ;
; data_in[1] ; 28    ; --       ; 2   ; 2                     ; 0                  ; no     ; LVTTL        ; Fitter               ;
; data_in[2] ; 20    ; --       ; 1   ; 2                     ; 0                  ; no     ; LVTTL        ; Fitter               ;
; data_in[3] ; 21    ; --       ; 1   ; 2                     ; 0                  ; no     ; LVTTL        ; Fitter               ;
+------------+-------+----------+-----+-----------------------+--------------------+--------+--------------+----------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                            ;