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📄 graycode.tan.rpt

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Timing Analyzer report for GRAYcode
Sun Mar 13 21:56:09 2005
Version 4.0 Build 190 1/28/2004 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Settings
  3. Timing Analyzer Summary
  4. tpd
  5. Minimum tpd
  6. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+----------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                               ;
+-----------------------------------------------------------------------------------------
; Option                                                ; Setting            ; From ; To ;
+-------------------------------------------------------+--------------------+------+----+
; Device name                                           ; EPM3032ALC44-4     ;      ;    ;
; Report IO Paths Separately                            ; Off                ;      ;    ;
; Ignore user-defined clock settings                    ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off read during write signal paths                ; On                 ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Run Minimum Analysis                                  ; On                 ;      ;    ;
; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Number of paths to report                             ; 200                ;      ;    ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+-----------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                           ;
+------------------------------------------------------------------------------------
; Type                   ; Slack ; Required Time ; Actual Time ; From ; To          ;
+------------------------+-------+---------------+-------------+------+-------------+
; Worst-case tpd         ; N/A   ; None          ; 4.500 ns    ; EN   ; data_out[4] ;
; Worst-case minimum tpd ; N/A   ; None          ; 4.500 ns    ; EN   ; data_out[4] ;
+------------------------+-------+---------------+-------------+------+-------------+


+------------------------------------------------------------------------+
; tpd                                                                    ;
+-------------------------------------------------------------------------
; Slack ; Required P2P Time ; Actual P2P Time ; From       ; To          ;
+-------+-------------------+-----------------+------------+-------------+
; N/A   ; None              ; 4.500 ns        ; EN         ; data_out[0] ;
; N/A   ; None              ; 4.500 ns        ; data_in[1] ; data_out[0] ;
; N/A   ; None              ; 4.500 ns        ; data_in[0] ; data_out[0] ;
; N/A   ; None              ; 4.500 ns        ; EN         ; data_out[1] ;
; N/A   ; None              ; 4.500 ns        ; data_in[2] ; data_out[1] ;
; N/A   ; None              ; 4.500 ns        ; data_in[1] ; data_out[1] ;
; N/A   ; None              ; 4.500 ns        ; EN         ; data_out[2] ;
; N/A   ; None              ; 4.500 ns        ; data_in[3] ; data_out[2] ;
; N/A   ; None              ; 4.500 ns        ; data_in[2] ; data_out[2] ;
; N/A   ; None              ; 4.500 ns        ; EN         ; data_out[3] ;
; N/A   ; None              ; 4.500 ns        ; data_in[3] ; data_out[3] ;
; N/A   ; None              ; 4.500 ns        ; EN         ; data_out[4] ;
+-------+-------------------+-----------------+------------+-------------+


+--------------------------------------------------------------------------------+
; Minimum tpd                                                                    ;
+---------------------------------------------------------------------------------
; Minimum Slack ; Required P2P Time ; Actual P2P Time ; From       ; To          ;
+---------------+-------------------+-----------------+------------+-------------+
; N/A           ; None              ; 4.500 ns        ; EN         ; data_out[4] ;
; N/A           ; None              ; 4.500 ns        ; data_in[3] ; data_out[3] ;
; N/A           ; None              ; 4.500 ns        ; EN         ; data_out[3] ;
; N/A           ; None              ; 4.500 ns        ; data_in[2] ; data_out[2] ;
; N/A           ; None              ; 4.500 ns        ; data_in[3] ; data_out[2] ;
; N/A           ; None              ; 4.500 ns        ; EN         ; data_out[2] ;
; N/A           ; None              ; 4.500 ns        ; data_in[1] ; data_out[1] ;
; N/A           ; None              ; 4.500 ns        ; data_in[2] ; data_out[1] ;
; N/A           ; None              ; 4.500 ns        ; EN         ; data_out[1] ;
; N/A           ; None              ; 4.500 ns        ; data_in[0] ; data_out[0] ;
; N/A           ; None              ; 4.500 ns        ; data_in[1] ; data_out[0] ;
; N/A           ; None              ; 4.500 ns        ; EN         ; data_out[0] ;
+---------------+-------------------+-----------------+------------+-------------+


+---------------------------+
; Timing Analyzer Messages  ;
+---------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.0 Build 190 1/28/2004 SJ Full Version
    Info: Processing started: Sun Mar 13 21:56:08 2005
Info: Command: quartus_tan --lower_priority --import_settings_files=off --export_settings_files=off GRAYcode -c GRAYcode
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Longest tpd from source pin EN to destination pin data_out[0] is 4.500 ns
    Info: 1: + IC(0.000 ns) + CELL(0.700 ns) = 0.700 ns; Loc. = Pin_24; Fanout = 12; PIN Node = 'EN'
    Info: 2: + IC(0.900 ns) + CELL(2.100 ns) = 3.700 ns; Loc. = LC1; Fanout = 4; COMB Node = 'i12~43'
    Info: 3: + IC(0.000 ns) + CELL(0.800 ns) = 4.500 ns; Loc. = Pin_4; Fanout = 0; PIN Node = 'data_out[0]'
    Info: Total cell delay = 3.600 ns ( 80.00 % )
    Info: Total interconnect delay = 0.900 ns ( 20.00 % )
Info: Shortest tpd from source pin EN to destination pin data_out[4] is 4.500 ns
    Info: 1: + IC(0.000 ns) + CELL(0.700 ns) = 0.700 ns; Loc. = Pin_24; Fanout = 12; PIN Node = 'EN'
    Info: 2: + IC(0.900 ns) + CELL(2.100 ns) = 3.700 ns; Loc. = LC6; Fanout = 1; COMB Node = 'EN~1'
    Info: 3: + IC(0.000 ns) + CELL(0.800 ns) = 4.500 ns; Loc. = Pin_9; Fanout = 0; PIN Node = 'data_out[4]'
    Info: Total cell delay = 3.600 ns ( 80.00 % )
    Info: Total interconnect delay = 0.900 ns ( 20.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Processing ended: Sun Mar 13 21:56:09 2005
    Info: Elapsed time: 00:00:00


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