expanddatabit.v

来自「Quartus下的数据扩展工程」· Verilog 代码 · 共 20 行

module ExpandDataBit(DataIn, DataOut);
	 
	 //define the length of input and output data
	 //the maximal lenthg is 64bit;
	 parameter InLength=8;
	 parameter OutLength=10;
    
	 input [InLength-1:0] DataIn;
    output [OutLength-1:0] DataOut;

	 reg [OutLength-1:0]DataOut;
	 reg [5:0]nCount;

	 always@(DataIn)
	 	begin
			DataOut<=DataIn;
			for(nCount=0;nCount<OutLength-InLength;nCount=nCount+1)
				DataOut[OutLength-1-nCount]<=(DataIn[InLength-1]==1)?1:0;
		end
endmodule