viterbi.vhd

VHDL 程序

-------------------------------------------------------------------------------
--  Copyrights (C) None.
-------------------------------------------------------------------------------
-- File       : viterbi.vhd
-- Entity     : Viterbi (Top Entity)
-- Author     : AROOSA ZAHID <[e-mail]>
-------------------------------------------------------------------------------
-- Description: Top module for the soft decision viterbi decoder
--              Following are the submodules for the the viterbi module
--              Butterfly Module, ROM, Handshake_fsm, control(fsm),
--              3 port register file (Built in LEON register file), 
--              register to hold the final result till it is read by output
----------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;

ENTITY viterbi IS
    PORT(clk: IN STD_LOGIC;
         resetN: IN STD_LOGIC;
         frame_ready: IN STD_LOGIC;
         send_dec: IN STD_LOGIC;
         code: IN STD_LOGIC_VECTOR(287 DOWNTO 0);
         frame_read: OUT STD_LOGIC;
         dec_ready: OUT STD_LOGIC;
         decision: OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
     END viterbi;
     
ARCHITECTURE struct OF viterbi IS
    COMPONENT butterfly
        GENERIC(trellis_depth:INTEGER;
                no_of_btrflys :INTEGER);
        PORT(curr_state: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
             trellis_index: IN INTEGER RANGE 0 TO (trellis_depth-1);
             btrfly_index: IN INTEGER RANGE 0 TO no_of_btrflys;
             valid_bits: IN STD_LOGIC_VECTOR(63 DOWNTO 0);
             recvd_code: IN STD_LOGIC_VECTOR(5 DOWNTO 0);
             ideal_code: IN STD_LOGIC_VECTOR(11 DOWNTO 0);
             in_met_down: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
             in_met_upp: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
             output_metric: OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
             in_dec_down: IN STD_LOGIC_VECTOR(95 DOWNTO 0);
             in_dec_upp: IN STD_LOGIC_VECTOR(95 DOWNTO 0);
             out_dec: OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
             min_metric: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
             decision: OUT STD_LOGIC_VECTOR((trellis_depth-1) DOWNTO 0));      
    END COMPONENT;
    
    ------------[ FSM ]--------------------------------------------- 
    COMPONENT control IS                   
        GENERIC(trellis_depth:INTEGER;
                no_of_btrflys :INTEGER);
       PORT(clk: IN STD_LOGIC;
        resetN: IN STD_LOGIC;
        min_metric:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        in_decision: IN STD_LOGIC_VECTOR((trellis_depth-1) DOWNTO 0);
        new_frame: IN STD_LOGIC;
        send_dec: IN STD_LOGIC;
        dec_out: OUT STD_LOGIC;
        trellis_index: OUT INTEGER RANGE 0 TO (trellis_depth-1);
        btrfly_index: OUT INTEGER RANGE 0 TO no_of_btrflys;
        code_index_low: OUT INTEGER RANGE 0 TO 282;
        code_index_high: OUT INTEGER RANGE 5 TO 287;
        valid_bits: OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
        rd_addrs1_regs1: OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
        rd_addrs2_regs1: OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
        wr_addrs_regs1: OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
        re1_regs1: OUT STD_LOGIC;
        re2_regs1: OUT STD_LOGIC;
        we_regs1: OUT STD_LOGIC;
        rd_addrs1_regs2: OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
        rd_addrs2_regs2: OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
        wr_addrs_regs2: OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
        re1_regs2: OUT STD_LOGIC;
        re2_regs2: OUT STD_LOGIC;
        we_regs2: OUT STD_LOGIC;
        addrs_rom: OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
        curr_state: OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
        decoded: OUT STD_LOGIC_VECTOR((trellis_depth-1) DOWNTO 0));        END COMPONENT;
     
    -------------------------[ ROM ]---------------------------------------------------------
    COMPONENT rom 
         PORT (
           add      : IN  STD_LOGIC_VECTOR(4 downto 0);  
           Data_Out : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));  
       END COMPONENT;
       
    ----------------------[ Register File ]--------------------------------------------------   
    COMPONENT generic_regfile_3p is
                generic (tech : integer; abits : integer; dbits : integer;
                         wrfst : integer; numregs : integer);
                port (
                  wclk   : in  std_ulogic;
                  waddr  : in  std_logic_vector((abits -1) downto 0);
                  wdata  : in  std_logic_vector((dbits -1) downto 0);
                  we     : in  std_ulogic;
                  rclk   : in  std_ulogic;
                  raddr1 : in  std_logic_vector((abits -1) downto 0);
                  re1    : in  std_ulogic;
                  rdata1 : out std_logic_vector((dbits -1) downto 0);
                  raddr2 : in  std_logic_vector((abits -1) downto 0);
                  re2    : in  std_ulogic;
                  rdata2 : out std_logic_vector((dbits -1) downto 0)
                );
        END COMPONENT;
            
    ---------------------[ Multiplexer ]------------------------------------------------------
        COMPONENT multiplex 
        GENERIC(SIZE:INTEGER);
            PORT(A:IN STD_LOGIC_VECTOR(SIZE-1 downto 0);
                 B:IN STD_LOGIC_VECTOR(SIZE-1 downto 0);
                 CTRL:IN STD_LOGIC;
                 Q:OUT STD_LOGIC_VECTOR(SIZE-1 downto 0)
                 );
        END COMPONENT;      
        
    -------------------[ Single Register Without a Reset ]---------------------------------------
        COMPONENT NR_Register IS
        GENERIC(size:INTEGER);
            PORT(d:IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
                 clk:IN STD_LOGIC;
                 enable:IN STD_LOGIC;
                 q:OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
                 );
        END COMPONENT;
        
    ------------------[ FSM for 4 Phase Handshake ]-------------------------------------------
        COMPONENT handshake IS
        PORT(clk       : IN STD_LOGIC;
             resetN    : IN STD_LOGIC;
             req_prev  : IN STD_LOGIC;
             ack_next  : IN STD_LOGIC;
             dec_rdy   : IN STD_LOGIC;
             frame_rdy : OUT STD_LOGIC;
             dec_ack   : OUT STD_LOGIC;
             req_next  : OUT STD_LOGIC;
             ack_prev  : OUT STD_LOGIC);
        END COMPONENT;
        
    -----------------[ Internal Signals ]-----------------------------------------------------
        SIGNAL t_index: INTEGER RANGE 0 TO 47;
        SIGNAL b_index: INTEGER RANGE 0 TO 32;
        SIGNAL s_vector: STD_LOGIC_VECTOR(1 DOWNTO 0);
        SIGNAL coded_input: STD_LOGIC_VECTOR(5 DOWNTO 0);
        SIGNAL ideal_rom: STD_LOGIC_VECTOR(11 DOWNTO 0);
        SIGNAL br_met_down: STD_LOGIC_VECTOR(15 DOWNTO 0);
        SIGNAL br_met_upp: STD_LOGIC_VECTOR(15 DOWNTO 0);
        SIGNAL path_metric: STD_LOGIC_VECTOR(15 DOWNTO 0);
        SIGNAL read_met1_regs1: STD_LOGIC_VECTOR(15 DOWNTO 0);
        SIGNAL read_met2_regs1: STD_LOGIC_VECTOR(15 DOWNTO 0);
        SIGNAL read_met1_regs2: STD_LOGIC_VECTOR(15 DOWNTO 0);
        SIGNAL read_met2_regs2: STD_LOGIC_VECTOR(15 DOWNTO 0);
        SIGNAL read_dec1_regs1: STD_LOGIC_VECTOR(95 DOWNTO 0);
        SIGNAL read_dec1_regs2: STD_LOGIC_VECTOR(95 DOWNTO 0);
        SIGNAL read_dec2_regs1: STD_LOGIC_VECTOR(95 DOWNTO 0);
        SIGNAL read_dec2_regs2: STD_LOGIC_VECTOR(95 DOWNTO 0);
        SIGNAL dec_down_rd: STD_LOGIC_VECTOR(95 DOWNTO 0);
        SIGNAL dec_upp_rd: STD_LOGIC_VECTOR(95 DOWNTO 0);
        SIGNAL dec_wr: STD_LOGIC_VECTOR(95 DOWNTO 0);
        SIGNAL min_met: STD_LOGIC_VECTOR(7 DOWNTO 0);
        SIGNAL regs1_addrs_rd1: STD_LOGIC_VECTOR(4 DOWNTO 0);
        SIGNAL regs1_addrs_rd2: STD_LOGIC_VECTOR(4 DOWNTO 0);
        SIGNAL regs1_addrs_wr: STD_LOGIC_VECTOR(4 DOWNTO 0);
        SIGNAL regs2_addrs_rd1: STD_LOGIC_VECTOR(4 DOWNTO 0);
        SIGNAL regs2_addrs_rd2: STD_LOGIC_VECTOR(4 DOWNTO 0);
        SIGNAL regs2_addrs_wr: STD_LOGIC_VECTOR(4 DOWNTO 0);
        SIGNAL regs1_re1: STD_LOGIC;
        SIGNAL regs1_re2: STD_LOGIC;
        SIGNAL regs1_we: STD_LOGIC;
        SIGNAL regs2_re1: STD_LOGIC;
        SIGNAL regs2_re2: STD_LOGIC;
        SIGNAL regs2_we: STD_LOGIC;
        SIGNAL valid_flags: STD_LOGIC_VECTOR(63 DOWNTO 0);
        SIGNAL trellis_vector: STD_LOGIC_VECTOR(5 DOWNTO 0);
        SIGNAL btrfly_vector: STD_LOGIC_VECTOR(5 DOWNTO 0);
        SIGNAL low_code_index: INTEGER RANGE 0 TO 282;
        SIGNAL high_code_index: INTEGER RANGE 5 TO 287;
        SIGNAL dec_out: STD_LOGIC;
        SIGNAL final_dec: STD_LOGIC_VECTOR(47 dOWNTO 0);
        SIGNAL rom_addrs: STD_LOGIC_VECTOR(4 dOWNTO 0);
        SIGNAL output: STD_LOGIC_VECTOR(47 DOWNTO 0);
        SIGNAL next_frame: STD_LOGIC;
        SIGNAL prev_ack: STD_LOGIC;
        SIGNAL next_req: STD_LOGIC;
        SIGNAL dec_ack: STD_LOGIC;
        
        BEGIN 
     
        hand_shake_fsm: handshake PORT MAP(clk,resetN,frame_ready,send_dec,dec_out,next_frame,dec_ack,next_req,prev_ack);
        ctrl:control GENERIC MAP(48,32)PORT MAP(clk,resetN,min_met,final_dec,next_frame,dec_ack,dec_out,t_index,b_index,low_code_index,high_code_index,valid_flags,regs1_addrs_rd1,regs1_addrs_rd2,regs1_addrs_wr,regs1_re1,regs1_re2,regs1_we,regs2_addrs_rd1,regs2_addrs_rd2,regs2_addrs_wr,regs2_re1,regs2_re2,regs2_we,rom_addrs,s_vector,output);
        dec_ready <= next_req;
        frame_read <= prev_ack;
        coded_input <= code(low_code_index+2 DOWNTO low_code_index) & code(high_code_index DOWNTO high_code_index-2);
        trellis_vector <= CONV_STD_LOGIC_VECTOR(t_index,6);
        btrfly_vector <= CONV_STD_LOGIC_VECTOR(b_index,6);
        ACS:butterfly GENERIC MAP(48,32)PORT MAP(s_vector,t_index,b_index,valid_flags,coded_input,ideal_rom,br_met_down,br_met_upp,path_metric,dec_down_rd,dec_upp_rd,dec_wr,min_met,final_dec);   
        rom_ideal: rom PORT MAP(rom_addrs,ideal_rom);
        regs_set1: generic_regfile_3p GENERIC MAP(0,5,16,1,32) PORT MAP(clk,regs1_addrs_wr,path_metric,regs1_we,clk,regs1_addrs_rd1,regs1_re1,read_met1_regs1,regs1_addrs_rd2,regs1_re2,read_met2_regs1);
        regs_set2: generic_regfile_3p GENERIC MAP(0,5,16,1,32) PORT MAP(clk,regs2_addrs_wr,path_metric,regs2_we,clk,regs2_addrs_rd1,regs2_re1,read_met1_regs2,regs2_addrs_rd2,regs2_re2,read_met2_regs2);
        mux_rd1_met: multiplex GENERIC MAP(16) PORT MAP(read_met1_regs1,read_met1_regs2,regs2_re1,br_met_down);
        mux_rd2_met: multiplex GENERIC MAP(16) PORT MAP(read_met2_regs1,read_met2_regs2,regs2_re1,br_met_upp);
        dec_matrix1: generic_regfile_3p GENERIC MAP(0,5,96,1,32) PORT MAP(clk,regs1_addrs_wr,dec_wr,regs1_we,clk,regs1_addrs_rd1,regs1_re1,read_dec1_regs1,regs1_addrs_rd2,regs1_re2,read_dec2_regs1);
        dec_matrix2: generic_regfile_3p GENERIC MAP(0,5,96,1,32) PORT MAP(clk,regs2_addrs_wr,dec_wr,regs2_we,clk,regs2_addrs_rd1,regs2_re1,read_dec1_regs2,regs2_addrs_rd2,regs2_re2,read_dec2_regs2);
        mux_rd1_dec: multiplex GENERIC MAP(96) PORT MAP(read_dec1_regs1,read_dec1_regs2,regs2_re1,dec_down_rd);
        mux_rd2_dec: multiplex GENERIC MAP(96) PORT MAP(read_dec2_regs1,read_dec2_regs2,regs2_re1,dec_upp_rd);
        dec_reg: NR_Register GENERIC MAP(48) PORT MAP(output,clk,dec_out,decision);
     
END struct;