compare1.vhd

来自「一本很好的关于学习VHDL的书,Fundamentals of Digital 」· VHDL 代码 · 共 19 行

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY compare1 IS
	PORT (	A, B 	: IN 	STD_LOGIC ;
			AeqB	: OUT 	STD_LOGIC ) ;
END compare1 ;

ARCHITECTURE Behavior OF compare1 IS
BEGIN
	PROCESS ( A, B )
	BEGIN
		AeqB <= '0' ;
		IF A = B THEN
			AeqB <= '1' ;
		END IF ;
	END PROCESS ;
END Behavior ;