example1.vhd

来自「一本很好的关于学习VHDL的书,Fundamentals of Digital 」· VHDL 代码 · 共 10 行

ENTITY example1 IS 
	PORT ( 	x1, x2, x3 	: IN 	BIT ; 
				f 		: OUT 	BIT ) ; 
END example1 ; 

ARCHITECTURE LogicFunc OF example1 IS 
BEGIN   
	f <= (x1 AND x2) OR (NOT x2 AND x3) ; 
END LogicFunc ;