videogenerator.vm

用lattice XP3 demo板设计的VGA信号发生器

//
// Written by Synplify
// Synplify 9.0.0, Build 253R.
// Mon Jun 18 08:11:33 2007
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "noname"
// file 1 "\c:\isptools6_1\synpbase\lib\vhd\std.vhd "
// file 2 "\d:\fpga\videog~1\videogenerator.vhd "
// file 3 "\c:\isptools6_1\synpbase\lib\vhd\std1164.vhd "
// file 4 "\c:\isptools6_1\synpbase\lib\vhd\numeric.vhd "

`timescale 100 ps/100 ps
module MACH_DFF (
  Q,
  D,
  CLK,
  R,
  S,
  NOTIFIER
);
output Q ;
input D ;
input CLK ;
input R ;
input S ;
input NOTIFIER ;
wire Q ;
wire D ;
wire CLK ;
wire R ;
wire S ;
wire NOTIFIER ;
wire un0 ;
wire un1 ;
wire VCC ;
wire GND ;
  assign #(1)  un0 = ~ S;
  assign #(1)  un1 = ~ R;
  assign VCC = 1'b1;
  assign GND = 1'b0;
  reg Q_r_e_g; // dffrs
  always @(posedge CLK or posedge un1 or posedge un0 )
    Q_r_e_g = #1 un1 ? 1'b0 : (un0 ? 1'b1 : D );
  assign Q = Q_r_e_g;
endmodule /* MACH_DFF */

module DFF (
  Q,
  D,
  CLK
);
output Q ;
input D ;
input CLK ;
wire Q ;
wire D ;
wire CLK ;
wire VCC ;
wire GND ;
  MACH_DFF INS4 (
	.Q(Q),
	.D(D),
	.CLK(CLK),
	.R(VCC),
	.S(VCC),
	.NOTIFIER(GND)
);
  assign VCC = 1'b1;
  assign GND = 1'b0;
endmodule /* DFF */

module IBUF (
  O,
  I0
);
output O ;
input I0 ;
wire O ;
wire I0 ;
wire VCC ;
wire GND ;
  assign #(1)  O = I0;
  assign VCC = 1'b1;
  assign GND = 1'b0;
endmodule /* IBUF */

module OBUF (
  O,
  I0
);
output O ;
input I0 ;
wire O ;
wire I0 ;
wire VCC ;
wire GND ;
  assign #(1)  O = I0;
  assign VCC = 1'b1;
  assign GND = 1'b0;
endmodule /* OBUF */

module AND2 (
  O,
  I0,
  I1
);
output O ;
input I0 ;
input I1 ;
wire O ;
wire I0 ;
wire I1 ;
wire VCC ;
wire GND ;
  assign VCC = 1'b1;
  assign GND = 1'b0;
  assign #(1)  O = I0  & I1 ;
endmodule /* AND2 */

module INV (
  O,
  I0
);
output O ;
input I0 ;
wire O ;
wire I0 ;
wire VCC ;
wire GND ;
  assign #(1)  O = ~ I0;
  assign VCC = 1'b1;
  assign GND = 1'b0;
endmodule /* INV */

module OR2 (
  O,
  I0,
  I1
);
output O ;
input I0 ;
input I1 ;
wire O ;
wire I0 ;
wire I1 ;
wire VCC ;
wire GND ;
  assign VCC = 1'b1;
  assign GND = 1'b0;
  assign #(1)  O = I0  | I1 ;
endmodule /* OR2 */

module XOR2 (
  O,
  I0,
  I1
);
output O ;
input I0 ;
input I1 ;
wire O ;
wire I0 ;
wire I1 ;
wire VCC ;
wire GND ;
  assign VCC = 1'b1;
  assign GND = 1'b0;
  assign #(1)  O = I0  ^ I1 ;
endmodule /* XOR2 */

module VideoGenerator (
  clk,
  UARTrx,
  UARTtx,
  VGAr,
  VGAg,
  VGAb,
  VGAh_cs,
  VGAv,
  VGAdena,
  NUMlocation,
  NUMdata,
  key
);
input clk ;
input UARTrx ;
output UARTtx ;
output [1:0] VGAr ;
output [1:0] VGAg ;
output [1:0] VGAb ;
output VGAh_cs ;
output VGAv ;
output VGAdena ;
output [3:0] NUMlocation ;
output [7:0] NUMdata ;
input key ;
wire clk ;
wire UARTrx ;
wire UARTtx ;
wire VGAh_cs ;
wire VGAv ;
wire VGAdena ;
wire key ;
wire [12:0] countforhorizontal;
wire [6:1] un1_countforph;
wire [6:0] countforph;
wire [12:0] countforvertical;
wire [5:0] countforcolor;
wire [6:0] countforph_4;
wire [12:1] un2_countforhorizontal_1;
wire [10:0] countforhorizontal_3;
wire [12:0] countforvertical_3;
wire [1:0] VGAr_5;
wire [1:0] VGAg_4;
wire [1:0] VGAb_4;
wire [5:0] countforcolor_2;
wire [12:1] un1_countforvertical;
wire [12:3] countforvertical_3_i_0;
wire [2:0] countforvertical_i_0;
wire [12:1] un1_countforvertical_i_0;
wire [12:2] un2_countforhorizontal_1_i_0;
wire [10:3] countforhorizontal_3_i_0;
wire [0:0] countforhorizontal_i_0;
wire [6:0] countforph_i_0;
wire [6:4] un1_countforph_i_0;
wire [1:0] VGAr_c;
wire [1:0] VGAg_c;
wire [1:0] VGAb_c;
wire [11:2] un1_countforvertical_i;
wire [5:2] countforvertical_3_i;
wire [1:0] countforhorizontal_3_i;
wire [10:10] un2_countforhorizontal_1_i;
wire pixelClock ;
wire N_2 ;
wire N_3 ;
wire N_4 ;
wire N_5 ;
wire N_6 ;
wire N_7 ;
wire N_8 ;
wire N_9 ;
wire N_10 ;
wire N_11 ;
wire N_12 ;
wire N_13 ;
wire N_14 ;
wire N_15 ;
wire N_16 ;
wire N_17 ;
wire N_18 ;
wire N_19 ;
wire N_20 ;
wire N_21 ;
wire N_22 ;
wire N_23 ;
wire N_24 ;
wire N_25 ;
wire N_26 ;
wire N_27 ;
wire N_28 ;
wire N_29 ;
wire N_30 ;
wire N_31 ;
wire N_32 ;
wire N_33 ;
wire N_34 ;
wire N_35 ;
wire N_36 ;
wire N_37 ;
wire N_38 ;
wire N_39 ;
wire N_40 ;
wire N_41 ;
wire N_42 ;
wire N_43 ;
wire N_44 ;
wire N_45 ;
wire N_46 ;
wire N_47 ;
wire N_48 ;
wire N_49 ;
wire GND ;
wire N_556 ;
wire N_384 ;
wire N_381 ;
wire N_400 ;
wire un77_pixelclock ;
wire N_397 ;
wire N_409 ;
wire N_406 ;
wire N_403 ;
wire N_419 ;
wire N_422 ;
wire N_434 ;
wire N_431 ;
wire N_437 ;
wire un7_pixelclock ;
wire un7_pixelclock_3 ;
wire N_289 ;
wire N_530 ;
wire N_446 ;
wire N_443 ;
wire N_440 ;
wire N_231 ;
wire un25_pixelclock ;
wire un33_pixelclock ;
wire un29_pixelclock ;
wire VGAv_2_sqmuxa ;
wire un11_pixelclock ;
wire N_309 ;
wire VGAv_2 ;
wire VGAv_2_f1 ;
wire VGAv_1_sqmuxa ;
wire VGAh_cs_i_m ;
wire N_374 ;
wire N_378 ;
wire N_387 ;
wire N_425 ;
wire N_428 ;
wire N_480 ;
wire N_483 ;
wire N_486 ;
wire N_135 ;
wire N_130 ;
wire N_139 ;
wire N_136 ;
wire N_547 ;
wire N_241 ;
wire N_238 ;
wire VGAdena_0_sqmuxa ;
wire un65_pixelclock ;
wire un63_pixelclock ;
wire un51_pixelclock_1 ;
wire VGAdena_0_sqmuxa_1 ;
wire N_1 ;
wire N_449 ;
wire N_459 ;
wire N_462 ;
wire N_489 ;
wire N_477 ;
wire N_474 ;
wire N_348 ;
wire N_129_1 ;
wire N_249 ;
wire N_125 ;
wire N_129 ;
wire N_252 ;
wire N_468 ;
wire N_465 ;
wire countforvertical_3_sn_N_2 ;
wire N_255 ;
wire N_253 ;
wire N_250 ;
wire N_471 ;
wire N_428_i ;
wire un25_pixelclock_i_0 ;
wire N_249_i_0 ;
wire VGAdena_i_0 ;
wire N_422_i_0 ;
wire VGAh_cs_i_0 ;
wire VGAv_1_sqmuxa_i_0 ;
wire un29_pixelclock_i_0 ;
wire pixelClock_i_0 ;
wire clk_i_0 ;
wire clk_c ;
wire VGAh_cs_c ;
wire VGAv_c ;
wire VGAdena_c ;
wire N_348_i ;
wire un33_pixelclock_i_0 ;
wire N_618 ;
wire N_129_1_i ;
wire N_622 ;
wire un33_pixelclock_6_i_0 ;
wire VGAdena_0_sqmuxa_1_i ;
wire N_1_i ;
wire N_627 ;
wire N_542_i_0 ;
wire N_547_i ;
wire N_11_i ;
wire un63_pixelclock_i_0 ;
wire un51_pixelclock_1_i_0 ;
wire N_635 ;
wire N_238_i ;
wire N_636 ;
wire N_136_i ;
wire N_639 ;
wire N_130_i ;
wire N_640 ;
wire VGAh_cs_i_m_i ;
wire VGAh_cs_3_iv_i_0 ;
wire VGAv_c_i ;
wire VGAv_2_sqmuxa_i ;
wire N_643 ;
wire N_309_i ;
wire un11_pixelclock_i_0 ;
wire N_647 ;
wire N_541_i_0 ;
wire N_556_i ;
wire N_555_i_0 ;
wire un7_pixelclock_1 ;
wire un7_pixelclock_2 ;
wire un25_pixelclock_1 ;
wire un29_pixelclock_1 ;
wire un29_pixelclock_2 ;
wire N_556_1 ;
wire N_556_2 ;
wire N_556_3 ;
wire un7_pixelclock_1_0 ;
wire un7_pixelclock_2_0 ;
wire un7_pixelclock_3_0 ;
wire un7_pixelclock_4 ;
wire un7_pixelclock_5 ;
wire un25_pixelclock_1_0 ;
wire un25_pixelclock_2 ;
wire un25_pixelclock_3 ;
wire un25_pixelclock_4 ;
wire un25_pixelclock_5 ;
wire un25_pixelclock_6 ;
wire VGAv_2_sqmuxa_1 ;
wire un11_pixelclock_i_0_1 ;
wire un11_pixelclock_i_0_2 ;
wire N_640_1 ;
wire N_547_1 ;
wire N_547_2 ;
wire N_238_1 ;
wire VGAdena_0_sqmuxa_1_0 ;
wire N_635_1 ;
wire N_635_2 ;
wire N_635_3 ;
wire N_635_4 ;
wire N_635_5 ;
wire N_635_6 ;
wire N_635_7 ;
wire un63_pixelclock_i_0_1 ;
wire un63_pixelclock_i_0_2 ;
wire un63_pixelclock_i_0_3 ;
wire un63_pixelclock_i_0_4 ;
wire un63_pixelclock_i_0_5 ;
wire un29_pixelclock_1_0 ;
wire un29_pixelclock_2_0 ;
wire un29_pixelclock_3 ;
wire un29_pixelclock_4 ;
wire un29_pixelclock_5 ;
wire un29_pixelclock_6 ;
wire un29_pixelclock_7 ;
wire un29_pixelclock_8 ;
wire un33_pixelclock_i_0_1 ;
wire un33_pixelclock_i_0_2 ;
wire un33_pixelclock_i_0_3 ;
wire un33_pixelclock_i_0_4 ;
wire un33_pixelclock_i_0_5 ;
wire un33_pixelclock_i_0_6 ;
wire N_555_i_0_1 ;
wire \countforvertical_3_0_8_.un3  ;
wire \countforvertical_3_0_8_.un1  ;
wire \countforvertical_3_0_8_.un0  ;
wire \countforvertical_3_0_6_.un3  ;
wire \countforvertical_3_0_6_.un1  ;
wire \countforvertical_3_0_6_.un0  ;
wire \countforvertical_3_0_5_.un3  ;
wire \countforvertical_3_0_5_.un1  ;
wire \countforvertical_3_0_5_.un0  ;
wire \countforvertical_3_0_4_.un3  ;
wire \countforvertical_3_0_4_.un1  ;
wire \countforvertical_3_0_4_.un0  ;
wire \countforvertical_3_0_3_.un3  ;
wire \countforvertical_3_0_3_.un1  ;
wire \countforvertical_3_0_3_.un0  ;
wire \countforvertical_3_0_2_.un3  ;
wire \countforvertical_3_0_2_.un1  ;
wire \countforvertical_3_0_2_.un0  ;
wire \countforvertical_0_4_.un3  ;
wire \countforvertical_0_4_.un1  ;
wire \countforvertical_0_4_.un0  ;
wire \countforvertical_3_8_.un3  ;
wire \countforvertical_3_8_.un1  ;
wire \countforvertical_3_8_.un0  ;
wire \countforvertical_3_6_.un3  ;
wire \countforvertical_3_6_.un1  ;
wire \countforvertical_3_6_.un0  ;
wire \countforvertical_3_5_.un3  ;
wire \countforvertical_3_5_.un1  ;
wire \countforvertical_3_5_.un0  ;
wire \countforvertical_3_3_.un3  ;
wire \countforvertical_3_3_.un1  ;
wire \countforvertical_3_3_.un0  ;
wire \countforvertical_3_2_.un3  ;
wire \countforvertical_3_2_.un1  ;
wire \countforvertical_3_2_.un0  ;
wire \countforvertical_3_0_12_.un3  ;
wire \countforvertical_3_0_12_.un1  ;
wire \countforvertical_3_0_12_.un0  ;
wire \countforvertical_3_0_7_.un3  ;
wire \countforvertical_3_0_7_.un1  ;
wire \countforvertical_3_0_7_.un0  ;
wire \countforvertical_0_2_.un3  ;
wire \countforvertical_0_2_.un1  ;
wire \countforvertical_0_2_.un0  ;
wire \countforvertical_0_3_.un3  ;
wire \countforvertical_0_3_.un1  ;
wire \countforvertical_0_3_.un0  ;
wire \countforvertical_0_5_.un3  ;
wire \countforvertical_0_5_.un1  ;
wire \countforvertical_0_5_.un0  ;
wire \countforvertical_0_6_.un3  ;
wire \countforvertical_0_6_.un1  ;
wire \countforvertical_0_6_.un0  ;
wire \countforvertical_3_0_1_.un3  ;
wire \countforvertical_3_0_1_.un1  ;
wire \countforvertical_3_0_1_.un0  ;
wire \countforvertical_3_0_9_.un3  ;
wire \countforvertical_3_0_9_.un1  ;
wire \countforvertical_3_0_9_.un0  ;
wire \countforhorizontal_0_11_.un3  ;
wire \countforhorizontal_0_11_.un1  ;
wire \countforhorizontal_0_11_.un0  ;
wire \VGAh_cs_0.un3  ;
wire \VGAh_cs_0.un1  ;
wire \VGAh_cs_0.un0  ;
wire \VGAv_0.un3  ;
wire \VGAv_0.un1  ;
wire \VGAv_0.un0  ;
wire \VGAdena_0.un3  ;
wire \VGAdena_0.un1  ;
wire \VGAdena_0.un0  ;
wire \countforhorizontal_0_5_.un3  ;
wire \countforhorizontal_0_5_.un1  ;
wire \countforhorizontal_0_5_.un0  ;
wire \countforhorizontal_0_1_.un3  ;
wire \countforhorizontal_0_1_.un1  ;
wire \countforhorizontal_0_1_.un0  ;
wire \countforhorizontal_0_0_.un3  ;
wire \countforhorizontal_0_0_.un1  ;
wire \countforhorizontal_0_0_.un0  ;
wire \countforvertical_3_0_11_.un3  ;
wire \countforvertical_3_0_11_.un1  ;
wire \countforvertical_3_0_11_.un0  ;
wire \countforvertical_0_0_.un3  ;
wire \countforvertical_0_0_.un1  ;
wire \countforvertical_0_0_.un0  ;
wire \countforvertical_0_1_.un3  ;
wire \countforvertical_0_1_.un1  ;
wire \countforvertical_0_1_.un0  ;
wire \countforhorizontal_0_3_.un3  ;
wire \countforhorizontal_0_3_.un1  ;
wire \countforhorizontal_0_3_.un0  ;
wire \countforhorizontal_0_12_.un3  ;
wire \countforhorizontal_0_12_.un1  ;
wire \countforhorizontal_0_12_.un0  ;
wire \countforvertical_0_12_.un3  ;
wire \countforvertical_0_12_.un1  ;
wire \countforvertical_0_12_.un0  ;
wire \countforvertical_0_11_.un3  ;
wire \countforvertical_0_11_.un1  ;
wire \countforvertical_0_11_.un0  ;
wire \countforvertical_0_7_.un3  ;
wire \countforvertical_0_7_.un1  ;
wire \countforvertical_0_7_.un0  ;
wire \countforvertical_0_8_.un3  ;
wire \countforvertical_0_8_.un1  ;
wire \countforvertical_0_8_.un0  ;
wire \countforhorizontal_0_10_.un3  ;
wire \countforhorizontal_0_10_.un1  ;
wire \countforhorizontal_0_10_.un0  ;
wire \countforvertical_3_0_10_.un3  ;
wire \countforvertical_3_0_10_.un1  ;
wire \countforvertical_3_0_10_.un0  ;
wire \countforcolor_0_1_.un3  ;
wire \countforcolor_0_1_.un1  ;
wire \countforcolor_0_1_.un0  ;
wire \countforcolor_0_2_.un3  ;
wire \countforcolor_0_2_.un1  ;
wire \countforcolor_0_2_.un0  ;
wire \countforcolor_0_3_.un3  ;
wire \countforcolor_0_3_.un1  ;
wire \countforcolor_0_3_.un0  ;
wire \countforcolor_0_4_.un3  ;
wire \countforcolor_0_4_.un1  ;
wire \countforcolor_0_4_.un0  ;
wire \countforcolor_0_5_.un3  ;
wire \countforcolor_0_5_.un1  ;
wire \countforcolor_0_5_.un0  ;
wire \countforph_0_3_.un3  ;
wire \countforph_0_3_.un1  ;
wire \countforph_0_3_.un0  ;
wire \countforhorizontal_3_0_.un3  ;
wire \countforhorizontal_3_0_.un1  ;
wire \countforhorizontal_3_0_.un0  ;
wire \countforhorizontal_3_10_.un3  ;
wire \countforhorizontal_3_10_.un1  ;
wire \countforhorizontal_3_10_.un0  ;
wire \countforvertical_0_9_.un3  ;
wire \countforvertical_0_9_.un1  ;
wire \countforvertical_0_9_.un0  ;
wire \countforvertical_0_10_.un3  ;
wire \countforvertical_0_10_.un1  ;
wire \countforvertical_0_10_.un0  ;
wire \VGAr_0_0_.un3  ;
wire \VGAr_0_0_.un1  ;
wire \VGAr_0_0_.un0  ;
wire \VGAr_0_1_.un3  ;
wire \VGAr_0_1_.un1  ;
wire \VGAr_0_1_.un0  ;
wire \VGAg_0_0_.un3  ;
wire \VGAg_0_0_.un1  ;